Oskar Mencer

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Spatial Programming with OpenSPL.

[BibT_eX]

[DOI]

Tobias Becker

Georgi Gaydadjiev

Proceedings of the FPGAs for Software Programmers, 2016

2015

Dataflow Computing in Extreme Performance Conditions.

[BibT_eX]

[DOI]

Diego Oriato

Stephen Girdlestone

Adv. Comput., 2015

Keynote 1 - From data to information to flow.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A Data Centric Perspective on Memory Placement.

[BibT_eX]

[DOI]

Yitzhak Birk

Proceedings of the 2015 International Symposium on Memory Systems, 2015

2014

Scaling Reverse Time Migration Performance through Reconfigurable Dataflow Engines.

[BibT_eX]

[DOI]

IEEE Micro, 2014

Real-Time Olivary Neuron Simulations on Dataflow Computing Machines.

[BibT_eX]

[DOI]

Catalin Bogdan Ciobanu

Chris I. De Zeeuw

Proceedings of the Supercomputing - 29th International Conference, 2014

A highly-efficient and green data flow engine for solving euler atmospheric equations.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

Finite-Difference Wave Propagation Modeling on Special-Purpose Dataflow Machines.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2013

Moving from petaflops to petadata.

[BibT_eX]

[DOI]

Veljko M. Milutinovic

Commun. ACM, 2013

Going to the wire: The next generation financial risk management platform.

[BibT_eX]

[DOI]

Ari Studnitzer

Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

2012

FISH: Fast Instruction SyntHesis for Custom Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Rapid computation of value and risk for derivatives portfolios.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2012

Maximum performance computing for exascale applications.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Dataflow supercomputing.

[BibT_eX]

[DOI]

Oliver Pell

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2011

Surviving the end of frequency scaling with reconfigurable dataflow computing.

[BibT_eX]

[DOI]

Oliver Pell

SIGARCH Comput. Archit. News, 2011

Beyond Traditional Microprocessors for Geoscience High-Performance Computing Applications.

[BibT_eX]

[DOI]

IEEE Micro, 2011

Finding the right level of abstraction for minimizing operational expenditure.

[BibT_eX]

[DOI]

Proceedings of the WHPCF'11, 2011

2010

FPGA Designs with Optimized Logarithmic Arithmetic.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Surviving the end of scaling of traditional micro processors in HPC.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010

A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

Accelerating Seismic Computations Using Customized Number Representations on FPGAs.

[BibT_eX]

[DOI]

Robert G. Clapp

EURASIP J. Embed. Syst., 2009

Evaluating Sampling Based Hotspot Detection.

[BibT_eX]

[DOI]

Qiang Wu

Proceedings of the Architecture of Computing Systems, 2009

2008

Guest Editorial: 20 Years of ASAP.

[BibT_eX]

[DOI]

Yvon Savaria

J. Signal Process. Syst., 2008

CHIPS: Custom Hardware Instruction Processor Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Reconfigurable design with clock gating.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Smart Enumeration: A Systematic Approach to Exhaustive Search.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Finding Speedup in Parallel Processors.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008

Optimizing residue arithmetic on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Power-Aware and Branch-Aware Word-Length Optimization.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

An Approach to Graph and Netlist Compression.

[BibT_eX]

[DOI]

Jeehong Yang

Serap A. Savari

Proceedings of the 2008 Data Compression Conference (DCC 2008), 2008

Fast custom instruction identification by convex subgraph enumeration.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007

Designing a Posture Analysis System with Hardware Implementation.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2007

Improving Bounds for FPGA Logic Minimization.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Instrumented Multi-Stage Word-Length Optimization.

[BibT_eX]

[DOI]

Ray C. C. Cheung

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems.

[BibT_eX]

[DOI]

Ray C. C. Cheung

Proceedings of the FPL 2007, 2007

Optimizing Logarithmic Arithmetic on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Optimizing instruction-set extensible processors under data bandwidth constraints.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

ASC: a stream compiler for computing with FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Accuracy-Guaranteed Bit-Width Optimization.

[BibT_eX]

[DOI]

George A. Constantinides

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Dynamic clock-frequencies for FPGAs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

A Reconfigurable Simulation Framework for Financial Computation.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

Towards optimal custom instruction processors.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

Comparing floating-point and logarithmic number representations for reconfigurable acceleration.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGAs, GPUs and the PS2 - A Single Programming Methodology.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills.

[BibT_eX]

[DOI]

Evgeny Fiksman

Yitzhak Birk

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA.

[BibT_eX]

[DOI]

Robert G. Dimond

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Automating processor customisation: optimised memory access and resource sharing.

[BibT_eX]

[DOI]

Robert G. Dimond

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Optimizing Hardware Function Evaluation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Custom Hardware Architectures for Posture Analysis.

[BibT_eX]

M. P. T. Juvonen

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools.

[BibT_eX]

[DOI]

Robert G. Dimond

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

MiniBit: bit-width optimization via affine arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Automating custom-precision function evaluation for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Compilers, 2005

2004

Parameterized High Throughput Function Evaluation for FPGAs.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2004

Adaptive range reduction for hardware function evaluation.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003

Design space exploration with A Stream Compiler.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Hardware Design with a Scripting Language.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Floating Point Unit Generation and Evaluation for FPGAs.

[BibT_eX]

[DOI]

Jian Liang

Russell Tessier

Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

PyHDL: Hardware Scripting with Python.

[BibT_eX]

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2002

Floating-point bitwidth analysis via automatic differentiation.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

HAGAR: Efficient Multi-context Graph Processors.

[BibT_eX]

[DOI]

Zhining Huang

Lorenz Huelsbergen

Proceedings of the Field-Programmable Logic and Applications, 2002

PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001

Object-oriented domain specific compilers for programming FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Parameterized Function Evaluation for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2001

Pipelined Function Evaluation on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000

Application of Reconfigurable CORDIC Architectures.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2000

StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2000

1999

Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment.

[BibT_eX]

[DOI]

Marco Platzner

Proceedings of the 32nd Annual Hawaii International Conference on System Sciences (HICSS-32), 1999

1998

Hardware software tri-design of encryption for mobile communication units.

[BibT_eX]

[DOI]

Martin Morf

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

PAM-Blox: High Performance FPGA Design for Adaptive Computing.

[BibT_eX]

[DOI]

Martin Morf