José Gabriel F. Coutinho

According to our database1, José Gabriel F. Coutinho authored at least 52 papers between 2002 and 2023.

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Bibliography

2023
MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Exploring Machine Learning Adoption in Customisable Processor Design.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

Preface ASAP 2023.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

2022
Meta-Programming Design-Flow Patterns for Automating Reusable Optimisations.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2022

2021
Scheduling Hardware-Accelerated Cloud Functions.
J. Signal Process. Syst., 2021

Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms.
ACM Trans. Reconfigurable Technol. Syst., 2021

Enhancing High-Level Synthesis Using a Meta-Programming Approach.
IEEE Trans. Computers, 2021

2020
Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

SLATE: Managing Heterogeneous Cloud Functions.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
Enhanced Heterogeneous Cloud: Transparent Acceleration and Elasticity.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Transparent Heterogeneous Cloud Acceleration.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Performance Estimation for Exascale Reconfigurable Dataflow Platforms.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Performance Prediction for Large-Scale Heterogeneous Platforms.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2016
Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach.
Softw. Pract. Exp., 2016

High performance in the cloud with FPGA groups.
Proceedings of the 9th International Conference on Utility and Cloud Computing, 2016

Relation-oriented resource allocation for multi-accelerator systems.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution.
SIGARCH Comput. Archit. News, 2015

A DevOps approach to integration of software components in an EU research project.
Proceedings of the 1st International Workshop on Quality-Aware DevOps, 2015

Protocols by Default - Safe MPI Code Generation Based on Session Types.
Proceedings of the Compiler Construction - 24th International Conference, 2015

2014
Cross Resource Optimisation of Database Functionality across Heterogeneous Processors.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Elastic Management of Reconfigurable Accelerators.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

HARNESS Project: Managing Heterogeneous Computing Resources for a Cloud Platform.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Controlling a complete hardware synthesis toolchain with LARA aspects.
Microprocess. Microsystems, 2013

Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A scalable design approach for stencil computation on reconfigurable clusters.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Aspect driven compilation for dataflow designs.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract).
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Specifying Compiler Strategies for FPGA-based Systems.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Controlling Hardware Synthesis with Aspects.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Resource-Efficient Designs Using an Aspect-Oriented Approach.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Experiments with the LARA aspect-oriented approach.
Proceedings of the Companion Volume of the 11th International Conference on Aspect-oriented Software Development, 2012

LARA: an aspect-oriented programming language for embedded systems.
Proceedings of the 11th International Conference on Aspect-oriented Software Development, 2012

2011
Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation.
Trans. High Perform. Embed. Archit. Compil., 2011

2010
HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.
IEEE Micro, 2010

Multiloop Parallelisation Using Unrolling and Fission.
Int. J. Reconfigurable Comput., 2010

2009
Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation.
Proceedings of the SOFSEM 2009: Theory and Practice of Computer Science, 2009

A high-level compilation toolchain for heterogeneous systems.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Optimising designs by combining model-based and pattern-based transformations.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Reconfigurable design with clock gating.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Unrolling-based loop mapping and scheduling.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Mapping and scheduling with task clustering for heterogeneous computing systems.
Proceedings of the FPL 2008, 2008

Power-Aware and Branch-Aware Word-Length Optimization.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007
Hardware development based on a parallel programming language.
PhD thesis, 2007

Designing a Posture Analysis System with Hardware Implementation.
J. VLSI Signal Process., 2007

Instrumented Multi-Stage Word-Length Optimization.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems.
Proceedings of the FPL 2007, 2007

2005
Customisable Hardware Compilation.
J. Supercomput., 2005

Custom Hardware Architectures for Posture Analysis.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2003
Source-directed transformations for hardware compilation.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

2002
Optimising and adapting high-level hardware designs.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002


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