Wing Chiu Tam

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2012

SLIDER: Simulation of Layout-Injected Defects for Electrical Responses.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Physically-Aware Analysis of Systematic Defects in Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2012

Yield Learning Through Physically Aware Diagnosis of IC-Failure Populations.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2012

2011

SLIDER: A fast and accurate defect simulation framework.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

To DFM or not to DFM?

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Evaluating yield and testing impact of sub-wavelength lithography.

[BibT_eX]

[DOI]

Wojciech Maly

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Systematic defect identification through layout snippet clustering.

[BibT_eX]

[DOI]

Osei Poku

Proceedings of the 2011 IEEE International Test Conference, 2010

Automatic classification of bridge defects.

[BibT_eX]

[DOI]

Jeffrey E. Nelson

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Controlling DPPM through Volume Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Automated failure population creation for validating integrated circuit diagnosis methods.

[BibT_eX]

[DOI]

Osei Poku

Proceedings of the 46th Design Automation Conference, 2009

2008

Precise failure localization using automated layout analysis of diagnosis candidates.

[BibT_eX]

[DOI]

Osei Poku