Wolfgang Meyer

According to our database, Wolfgang Meyer authored at least 9 papers between 1992 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level Descriptions.

Andrew Seawright, Wolfgang Meyer

Proceedings of the 35th Conference on Design Automation, 1998

1997

Design and Synthesis of Array Structured Telecommunication Processing Applications.

Wolfgang Meyer, Andrew Seawright, Fumiya Tada

Proceedings of the 34st Conference on Design Automation, 1997

1996

A system for compiling and debugging structured data processing controllers.

Andrew Seawright, Joseph Buck, Ulrich Holtmann, Wolfgang Meyer, Barry M. Pangrle, Rob Verbrugghe

Proceedings of the conference on European design automation, 1996

1995

Active timing multilevel fault-simulation with switch-level accuracy.

Wolfgang Meyer, Raul Camposano

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994

Hierarchische Mehr-Ebenen-Fehlersimulation mit Modellen der Schalter-Ebene.

Wolfgang Meyer

PhD thesis, 1994

1993

Fault behavior and testability of asynchronous CMOS circuits.

Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser, Raul Camposano

Microprocess. Microprogramming, 1993

CMOS Bridges and Resistive Transistor Faults: I_DDQ versus Delay Effects.

Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy.

Wolfgang Meyer, Raul Camposano

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents.

Uwe Hübner, Wolfgang Meyer, Heinrich Theodor Vierhaus

Microprocess. Microprogramming, 1992