Wontak Han

According to our database, Wontak Han authored at least 6 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

SAL-PIM: A Subarray-level Processing-in-Memory Architecture with LUT-based Linear Interpolation for Transformer-based Text Generation.

Wontak Han, Hyunjun Cho, Donghyuk Kim, Joo-Young Kim

CoRR, 2024

2023

T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training.

Jaehoon Heo, Junsoo Kim, Sukbin Lim, Wontak Han, Joo-Young Kim

IEEE J. Solid State Circuits, March, 2023

Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics.

Donghyuk Kim, Jae-Young Kim, Wontak Han, Jongsoon Won, Haerang Choi, Yongkee Kwon, Joo-Young Kim

CoRR, 2023

SP-PIM: A 22.41TFLOPS/W, 8.81Epochs/Sec Super-Pipelined Processing-In-Memory Accelerator with Local Error Prediction for On-Device Learning.

Jung-Hoon Kim, Jaehoon Heo, Wontak Han, Jaeuk Kim, Joo-Young Kim

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Design of Processing-in-Memory With Triple Computational Path and Sparsity Handling for Energy-Efficient DNN Training.

Wontak Han, Jaehoon Heo, Junsoo Kim, Sukbin Lim, Joo-Young Kim

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

T-PIM: A 2.21-to-161.08TOPS/W Processing-In-Memory Accelerator for End-to-End On-Device Training.

Jaehoon Heo, Junsoo Kim, Wontak Han, Sukbin Lim, Joo-Young Kim

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022