Lan-Da Van

According to our database1, Lan-Da Van authored at least 62 papers between 1999 and 2021.

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Bibliography

2021
Hardware-Oriented Memory-Limited Online Artifact Subspace Reconstruction (HMO-ASR) Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Things in the air: tagging wearable IoT information on drone videos.
Discov. Internet Things, 2021

An Edge-Controlled Outdoor Autonomous UAV for Colorwise Safety Helmet Detection and Counting of Workers in Construction Sites.
Proceedings of the 94th IEEE Vehicular Technology Conference, 2021

Trajectory-Based Dynamic Handwriting Recognition Using Fusion Neural Network.
Proceedings of the 2021 International Conference on Technologies and Applications of Artificial Intelligence, 2021

A Computation-Aware TPL Utilization Procedure for Parallelizing the FastICA Algorithm on a Multi-Core CPU.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

Data Fusion Driven Lane-level Precision Data Transmission for V2X Road Applications.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

2020
An Intelligent Elevator Development and Management System.
IEEE Syst. J., 2020

Green Elevator Scheduling Based on IoT Communications.
IEEE Access, 2020

2019
PlantTalk: A Smartphone-Based Intelligent Hydroponic Plant Box.
Sensors, 2019

Demo: Tagging IoT Data in a Drone View.
Proceedings of the 25th Annual International Conference on Mobile Computing and Networking, 2019

Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation.
Proceedings of the IEEE International Conference on Acoustics, 2019

2018
Efficient Progressive Radiance Estimation Engine Architecture and Implementation for Progressive Photon Mapping.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

FPGA-Oriented Real-Time EMD-Based Breath Signal Processing System on ARM11 MPCore Platform.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Type-4 2-D Diagonal and Four-Fold Rotational Symmetry Digital Filter Architectures.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Analyzing students' attention in class using wearable devices.
Proceedings of the 18th IEEE International Symposium on A World of Wireless, 2017

New 2-D filter architectures with quadrantal symmetry and octagonal symmetry and their error analysis.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Qnalyzer: Queuing Recognition Using Accelerometer and Wi-Fi Signals.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

Type-3 2-D multimode IIR filter architecture and the corresponding symmetry filter's error analysis.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

New 2-D quadrantal- and diagonal-symmetry filter architectures using delta operator.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing.
J. Signal Process. Syst., 2016

Intelligent Plant Care Hydroponic Box Using IoTtalk.
Proceedings of the 2016 IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2016

2014
General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry.
Multidimens. Syst. Signal Process., 2014

Continuous Human Location and Posture Tracking by Multiple Depth Sensors.
Proceedings of the 2014 IEEE International Conference on Internet of Things, 2014

Implementation of a human-centric GUI for next-generation intensive care unit.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2014

Multiple stopping criteria and high-precision EMD architecture implementation for Hilbert-Huang transform.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
Design of 2-D digital filters with almost quadrantal symmetric magnitude response without 1-D separable denominator factor constraint.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Area-efficient 2-D digital filter architectures possessing diagonal and four-fold rotational symmetries.
Proceedings of the 9th International Conference on Information, 2013

2012
Delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the quadrantal symmetry.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Efficient Detection Algorithms for MIMO Communication Systems.
J. Signal Process. Syst., 2011

Energy-Efficient FastICA Implementation for Biomedical Signal Separation.
IEEE Trans. Neural Networks, 2011

A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Power-Efficient and Cost-Effective 2-D Symmetry Filter Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009
Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers.
IEEE Trans. Computers, 2009

Low Complexity Subdivision Algorithm to Approximate Phong Shading using Forward Difference.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2-D Digital Filter Architectures without Global Broadcast and Some Symmetry Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A New VLSI 2-D Fourfold-rotational-symmetry Filter Architecture Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A Grouped-Iterative Framework for MIMO Detection.
Proceedings of the 68th IEEE Vehicular Technology Conference, 2008

Reconfigurable Depth Buffer Compression Design for 3D Graphics System.
Proceedings of the 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 2008

Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Anticipatory access pipeline design for phased cache.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Design of multi-mode depth buffer compression for 3D graphics system.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

A new VLSI 2-D diagonal-symmetry filter architecture design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Adaptive Low-Error Fixed-Width Booth Multipliers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Classification of Driver's Cognitive Responses Using Nonparametric Single-trial EEG Analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

A cost-effective reconfigurable accelerator for platform-based SOC design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Generalized Low-Error Area-Efficient Fixed-Width Multipliers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A framework for the design of error-aware power-efficient fixed-width Booth multipliers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

High-performance low-complexity bit-plane coding scheme for MPEG-4 FGS.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

2004
High-speed area-efficient recursive DFT/IDFT architectures.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A high-performance area-aware DSP processor architecture for video codecs.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

2002
A new 2-D systolic digital filter architecture without global broadcast.
IEEE Trans. Very Large Scale Integr. Syst., 2002

A generalized methodology for lower-error area-efficient fixed-width multipliers.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR).
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A new VLSI architecture without global broadcast for 2-D digital filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Design of a lower-error fixed-width multiplier for speech processing application.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A tree-systolic array of DLMS adaptive filter.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999


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