Lan-Da Van
Orcid: 0000-0001-5673-1193
According to our database1,
Lan-Da Van
authored at least 67 papers
between 1999 and 2023.
Collaborative distances:
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Bibliography
2023
Proceedings of the NOMS 2023, 2023
2022
Found. Trends Signal Process., 2022
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022
Accuracy-Time Efficient Hyperparameter Optimization Using Actor-Critic-based Reinforcement Learning and Early Stopping in OpenAI Gym Environment.
Proceedings of the IEEE International Conference on Internet of Things and Intelligence Systems, 2022
Proceedings of the IEEE International Conference on Industrial Technology, 2022
2021
Hardware-Oriented Memory-Limited Online Artifact Subspace Reconstruction (HMO-ASR) Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Discov. Internet Things, 2021
An Edge-Controlled Outdoor Autonomous UAV for Colorwise Safety Helmet Detection and Counting of Workers in Construction Sites.
Proceedings of the 94th IEEE Vehicular Technology Conference, 2021
Proceedings of the 2021 International Conference on Technologies and Applications of Artificial Intelligence, 2021
A Computation-Aware TPL Utilization Procedure for Parallelizing the FastICA Algorithm on a Multi-Core CPU.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021
2020
2019
Proceedings of the 25th Annual International Conference on Mobile Computing and Networking, 2019
Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation.
Proceedings of the IEEE International Conference on Acoustics, 2019
2018
Efficient Progressive Radiance Estimation Engine Architecture and Implementation for Progressive Photon Mapping.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
FPGA-Oriented Real-Time EMD-Based Breath Signal Processing System on ARM11 MPCore Platform.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
Proceedings of the 18th IEEE International Symposium on A World of Wireless, 2017
New 2-D filter architectures with quadrantal symmetry and octagonal symmetry and their error analysis.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE Global Communications Conference, 2017
Type-3 2-D multimode IIR filter architecture and the corresponding symmetry filter's error analysis.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing.
J. Signal Process. Syst., 2016
Proceedings of the 2016 IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2016
2014
General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry.
Multidimens. Syst. Signal Process., 2014
Proceedings of the 2014 IEEE International Conference on Internet of Things, 2014
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2014
Multiple stopping criteria and high-precision EMD architecture implementation for Hilbert-Huang transform.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2013
Design of 2-D digital filters with almost quadrantal symmetric magnitude response without 1-D separable denominator factor constraint.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Area-efficient 2-D digital filter architectures possessing diagonal and four-fold rotational symmetries.
Proceedings of the 9th International Conference on Information, 2013
2012
Delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the quadrantal symmetry.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
J. Signal Process. Syst., 2011
IEEE Trans. Neural Networks, 2011
A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2009
IEEE Trans. Computers, 2009
Low Complexity Subdivision Algorithm to Approximate Phong Shading using Forward Difference.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2-D Digital Filter Architectures without Global Broadcast and Some Symmetry Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the 68th IEEE Vehicular Technology Conference, 2008
Proceedings of the 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 2008
Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Classification of Driver's Cognitive Responses Using Nonparametric Single-trial EEG Analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
A framework for the design of error-aware power-efficient fixed-width Booth multipliers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005
2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A high-performance area-aware DSP processor architecture for video codecs.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999