Wuudiann Ke

According to our database, Wuudiann Ke authored at least 12 papers between 1988 and 1996.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1996

Backplane Interconnect Test in a Boundary-Scan Environment.

Wuudiann Ke

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Hybrid Pin Control Using Boundary-Scan And Its Applications.

Wuudiann Ke

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Delay-testable implementations of symmetric functions.

Wuudiann Ke, Premachandran R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Path-delay-fault testable nonscan sequential circuits.

Wuudiann Ke, Premachandran R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Synthesis of Delay-Verifiable Combinational Circuits.

Wuudiann Ke, Premachandran R. Menon

IEEE Trans. Computers, 1995

Multifault and delay-fault testability of multilevel circuits.

Wuudiann Ke, Premachandran R. Menon

J. Electron. Test., 1995

Multifault testability of delay-testable circuits.

Wuudiann Ke, Premachandran R. Menon

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus.

Wuudiann Ke, Duy Le, Najmi T. Jarwala

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

Realization of fully path-delay-fault testable non-scan sequential circuits.

Wuudiann Ke, Premachandran R. Menon

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Delay-Verifiability of Combinational Circuits Based on Primitive Faults.

Wuudiann Ke, Premachandran R. Menon

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Synthesis of Delay-Verifiable Two-Level Circuits.

Wuudiann Ke, Premachandran R. Menon

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1988

A fast fault simulation algorithm for combinational circuits.

Wuudiann Ke, Sharad C. Seth, Bhargab B. Bhattacharya

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988