Xander Pottier

Orcid: 0009-0001-0072-7731

According to our database¹, Xander Pottier authored at least 4 papers between 2024 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2026

Area-Efficient LUT-Based Multipliers for AMD Versal FPGAs.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2026

2025

SMOOTHIE: (Multi-)Scalar Multiplication Optimizations On TFHE.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2025

Head Start: Digit Extraction in TFHE from MSB to LSB.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2025

2024

OPTIMSM: FPGA hardware accelerator for Zero-Knowledge MSM.

[BibT_eX]

[DOI]

Michiel Van Beirendonck

Ingrid Verbauwhede

IACR Cryptol. ePrint Arch., 2024

Xander Pottier

Timeline

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On csauthors.net:

Bibliography

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