Xianzeng Guo
According to our database1,
Xianzeng Guo authored at least 5 papers
between 2025 and 2026.
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Bibliography
2026
Proceedings of the Design, Automation & Test in Europe Conference, 2026
Input Sparsity Aware In-Memory Computing Macro Based on SOT-MRAM Multi-Level Cell for Efficient Deep Neural Network Acceleration.
Proceedings of the Design, Automation & Test in Europe Conference, 2026
2025
Technically Feasible Robust Complementary SOT-MRAM Design for Improving the Area and Energy Efficiency.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025
Robust and Efficient NAND-Like TST-MRAM with Parallel Write/Read Operations and Reconfigurable PUF Mode.
Proceedings of the 26th International Symposium on Quality Electronic Design, 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025