Chao Wang

According to our database, Chao Wang authored at least 26 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

BaM-CIM: A High Throughput Booth Algorithm-Based In-MRAM Computing Macro Using Hybrid VGSOT-MTJ/GAA-CNTFET.

Chenghang Li, Zhongzhen Tong, Yulong Qiu, Jiye Yao, Chao Wang, Zhaohao Wang, Xiaoyang Lin, Weisheng Zhao

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026

Multi-Retention and Bit-Level Approximate STT-MRAM for High-Efficiency AI Applications.

Yulong Qiu, Chao Wang, Weimeng Zhao, Zhongzhen Tong, Zhaohao Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

MEPUF: A Lightweight and ML-Resistant Strong PUF Integrating Dual-Mode MRAM and Configurable AES for Reliable UAVs.

Jiaxin Li, Bi Wang, Yan Qiao, Luyao Shi, Chao Wang, Zhaohao Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

Highly Energy-Efficient In-Memory Computing Architecture Based on VGSOT-MRAM for Reconfigurable BNN/TNN Acceleration.

Qihang Gao, Chao Wang, Chenghang Li, Zhongzhen Tong, Zhaohao Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A Low Power and High Reliability Nonvolatile SRAM Using In-Plane VGSOT-MRAM with Pre-Charge Restore Scheme.

Xiaoyang Xu, Chenyi Wang, Zhongzhen Tong, Mingche Li, Weimeng Zhao, Zhongkui Zhang, Yaling Wang, Chao Wang, Zhaohao Wang

Proceedings of the Design, Automation & Test in Europe Conference, 2026

High-Performance and High-Density NAND-Like SOT-MRAM for FinFET Technology Nodes.

Chao Wang, Xianzeng Guo, Luman Xiang, Zhaohao Wang, Weisheng Zhao

Proceedings of the Design, Automation & Test in Europe Conference, 2026

Input Sparsity Aware In-Memory Computing Macro Based on SOT-MRAM Multi-Level Cell for Efficient Deep Neural Network Acceleration.

Chao Wang, Qihang Gao, Xianzeng Guo, Zhongzhen Tong, Zhaohao Wang, Weisheng Zhao

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

A Self-Decryption Pass Transistor Logic-Based In-MRAM Computing Macro Using Hybrid VGSOT-MTJ/GAA-CNTFET.

Zhongzhen Tong, Sifan Sun, Kaili Zhang, Chenghang Li, Jiye Yao, Yulong Qiu, Chao Wang, Zhaohao Wang, Ke Zhang, Amara Amara, Xiaoyang Lin, Weisheng Zhao

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

Technically Feasible Robust Complementary SOT-MRAM Design for Improving the Area and Energy Efficiency.

Chao Wang, Zhongkui Zhang, Xiaoyang Xu, Xianzeng Guo, Qihang Gao, Zhaohao Wang, Weisheng Zhao

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025

A Novel Radiation-Hardened, Speed and Power Optimized Nonvolatile Latch for Aerospace Applications.

Shixing Li, Chenyi Wang, Zhongzhen Tong, Chao Wang, Bi Wang, Zhaohao Wang

IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

Thermal-Compensated MRAM Sensing: Dynamic TMR Stabilization Across Wide Temperature Range.

Tuo Zhang, Xinpeng Jiang, Chao Wang, Bi Wang, Hongxi Liu, Kaihua Cao, Xuan Li, Hui Jin, Geifei Wang, Zhaohao Wang, He Zhang, Weisheng Zhao

Proceedings of the 14th International Conference on Modern Circuits and Systems Technologies, 2025

Robust and Efficient NAND-Like TST-MRAM with Parallel Write/Read Operations and Reconfigurable PUF Mode.

Songhan Zhang, Xianzeng Guo, Yaling Wang, Chao Wang, Bi Wang, Zhaohao Wang

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance.

Yulong Qiu, Chao Wang, Zhongzhen Tong, Siyuan Cheng, Yueting Li, Zhaohao Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Quantitative Framework for Autocorrelation Analysis and Modeling Resistance Assessment of Physically Unclonable Functions.

Yuan Ma, Bi Wang, Chao Wang, Zhaohao Wang

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2025

2024

BSTCIM: A Balanced Symmetry Ternary Fully Digital In-MRAM Computing Macro for Energy Efficiency Neural Network.

Zhongzhen Tong, Chenghang Li, Chao Wang, Suteng Zhao, Qianyong Peng, Zhenyu Yan, Siqi Zhang, Daming Zhou, Zhaohao Wang, Xiaoyang Lin, Weisheng Zhao

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM.

Chao Wang, Zhaohao Wang, Shixing Li, Zhongkui Zhang, Youguang Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks.

Chao Wang, Zhaohao Wang, Zhongkui Zhang, Youguang Zhang, Weisheng Zhao

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Process and Design Considerations for Spin Orbit Torque MRAM.

Zhaohao Wang, Chao Wang, Min Wang, Chenyi Wang, Kaihua Cao, Chenlin Xu, Cong Zhang, Yunpeng Li, Hongxi Liu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

2023

Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process.

Chao Wang, Zhaohao Wang, Zhongkui Zhang, Jiagao Feng, Youguang Zhang, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

A Robust Time-based Error-Proofing Readout Scheme for MRAM.

Qianlei Ou, Shixing Li, Chao Wang, He Zhang, Zhaohao Wang

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

2022

Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM.

Zhengyi Hou, Zhaohao Wang, Chao Wang, Min Wang, You Wang, Xueyan Wang, Cenlin Duan, Jianlei Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Parallel Computing in Memory Paradigm based on Reconfigurable Spin-Orbit Torque.

Zhongkui Zhang, Chao Wang, Zhaohao Wang

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

2021

Computing-in-Memory Paradigm Based on STT-MRAM with Synergetic Read/Write-Like Modes.

Chao Wang, Zhaohao Wang, Youguang Zhang, Weisheng Zhao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.

Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories.

Bi Wu, Chao Wang, Zhaohao Wang, Ying Wang, Deming Zhang, Dijun Liu, Youguang Zhang, Xiaobo Sharon Hu

IEEE Trans. Circuits Syst., 2020

Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method.

Chao Wang, Zhaohao Wang, Yansong Xu, Jianlei Yang, Youguang Zhang, Weisheng Zhao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020