Xiao Wang

According to our database, Xiao Wang authored at least 10 papers between 2016 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy.

Meng Ni, Xiao Wang, Fule Li, Woogeun Rhee, Zhihua Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation.

Meng Ni, Xiao Wang, Fule Li, Zhihua Wang

IEEE Trans. Very Large Scale Integr. Syst., 2021

2020

A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction.

Peilin Yang, Xiao Wang, Chengwei Wang, Fule Li, Hanjun Jiang, Zhihua Wang

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs.

Xiao Wang, Fule Li, Zhihua Wang

IEEE Trans. Circuits Syst., 2020

A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC.

Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique.

Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019

A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration.

Xiao Wang, Fule Li, Wen Jia, Zhihua Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2019

2018

A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process.

Xiao Wang, Chengwei Wang, Fule Li, Zhihua Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique.

Chengwei Wang, Xiao Wang, Yang Ding, Fule Li, Zhihua Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016

A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs.

Xiao Wang, Fule Li, Zhihua Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016