Xiao Xiang

According to our database, Xiao Xiang authored at least 15 papers between 2012 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

FFCNN: A Deep Neural Network for Surface Defect Detection of Magnetic Tile.

Luofeng Xie, Xiao Xiang, Huining Xu, Ling Wang, Lijun Lin, Guofu Yin

IEEE Trans. Ind. Electron., 2021

Equal-slope baud-rate CDR algorithm with optimized eye opening.

Xiao Xiang, Weixin Gai, Ai He, Hang Zhou, Dong Yanchi

Microelectron. J., 2021

A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer.

Dong Yanchi, Weixin Gai, Xiao Xiang, Haowei Niu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2019

An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation.

Xiao Xiang, Weixin Gai, Linqi Shi, Ai He, Kai Sheng

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs.

Ai He, Weixin Gai, Yufan Feng, Zhongzhu Pu, Xiao Xiang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS.

Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang, Kai Sheng, Ai He

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor.

Linqi Shi, Weixin Gai, Xiaoting Zhi, Liangxiao Tang, Xiao Xiang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor.

Linqi Shi, Weixin Gai, Jichao Huang, Liangxiao Tang, Xiao Xiang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery.

Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

A 1.27mW 20Gbps 1: 16 DEMUX with a symmetrical-edge-delay sense amplifier.

Shihao Li, Weixin Gai, Xiao Xiang, Liangxiao Tang, Jichao Huang, Tong Zhao, Xiaoting Zhi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014

A centralized adaptive hybrid routing mechanism for Ad Hoc networks.

Jiaqi Xu, Chunxiu Xu, Xijie Zhang, Xiao Xiang

Proceedings of the 2014 International Symposium on Wireless Personal Multimedia Communications, 2014

Research on High-Speed Railway model for train-ground MIMO channel.

Xiao Xiang, Muqing Wu, Ruojun Zhao, Jiaqi Xu, Xin Su

Proceedings of the 2014 International Symposium on Wireless Personal Multimedia Communications, 2014

Comparative analysis on fading characteristics of the LTE-R channel in viaduct and hilly terrain scenarios.

Xiangli Lin, Chunxiu Xu, Siyu Zhang, Ruojun Zhao, Xiao Xiang

Proceedings of the 2014 International Symposium on Wireless Personal Multimedia Communications, 2014

Measurement and Modeling of the LTE Train-Ground Channel for High-Speed Railway in Viaduct Scenario.

Ruojun Zhao, Muqing Wu, Xiao Xiang, Jiaqi Yang

Proceedings of the IEEE 80th Vehicular Technology Conference, 2014

2012

A Local World Evolving Model for Energy-Constrained Wireless Sensor Networks.

Nan Jiang, Chen Huan, Xiao Xiang

Int. J. Distributed Sens. Networks, 2012