Liangxiao Tang

According to our database1, Liangxiao Tang authored at least 8 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2018
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 1.27mW 20Gbps 1: 16 DEMUX with a symmetrical-edge-delay sense amplifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015


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