Xiaorong Luo

According to our database, Xiaorong Luo authored at least 10 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Improvement of reverse conduction characteristic and single event effect for a novel vertical GaN field effect transistor with an integrated MOS-channel diode.

Xintong Xie, Shuxiang Sun, Zhijia Zhao, Pengfei Zhang, Jie Wei, Xin Zhou, Jingyu Shen, Jinpeng Qiu, Xiaorong Luo

Microelectron. J., February, 2024

2023

High voltage GaN vertical FinFET with a compatible integrated fin diode for low reverse conduction loss.

Zhijia Zhao, Yuxi Wei, Tao Sun, Kemeng Yang, Jie Wei, Yanjiang Jia, Siyu Deng, Xiaorong Luo, Bo Zhang

Microelectron. J., 2023

2022

Novel SiC SBD-wall-integrated trench MOSFET with a semi-superjunction and split trench gate.

Xiaorong Luo, Junyue Huang, Xu Song, Qinfeng Jiang, Jie Wei, Jian Fang, Fei Yang

Sci. China Inf. Sci., 2022

Sign-changing solutions to the critical Choquard equation.

Xiaorong Luo, Anmin Mao

Appl. Math. Lett., 2022

2021

TOC determination of Zhangjiatan shale of Yanchang formation, Ordos Basin, China, using support vector regression and well logs.

Xin Liu, Yuhong Lei, Xiaorong Luo, Xiangzeng Wang, Kaiyuan Chen, Ming Cheng, Jintao Yin

Earth Sci. Informatics, 2021

2019

Simulation of a high-performance enhancement-mode HFET with back-to-back graded AlGaN layers.

Fu Peng, Chao Yang, Siyu Deng, Dongya Ouyang, Bo Zhang, Jie Wei, Xiaorong Luo

Sci. China Inf. Sci., 2019

2018

High-voltage trench-gate hole-gas enhancement-mode HEMT with multi-conduction channels.

Chao Yang, Xiaorong Luo, Siyu Deng, Fu Peng, Bo Zhang

Sci. China Inf. Sci., 2018

2017

Ultralow power loss integratable high-voltage MOSFETs.

Xiaorong Luo, Weiwei Ge, Bo Zhang

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Novel high voltage RESURF AlGaN/GaN HEMT with charged buffer layer.

Jiayun Xiong, Chao Yang, Jie Wei, Junfeng Wu, Bo Zhang, Xiaorong Luo

Sci. China Inf. Sci., 2016

2013

Novel High voltage silicon-on-insulator Device with Composite dielectric buried Layer.

Jie Fan, Xiaorong Luo, Bo Zhang, Zhaoji Li

J. Circuits Syst. Comput., 2013