Xiongxin Zhao

According to our database1, Xiongxin Zhao authored at least 16 papers between 2010 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Perceptual Image Compression Using Relativistic Average Least Squares GANs.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2021

2016
Heterogeneous Multi-task Learning on Non-overlapping Datasets for Facial Landmark Detection.
Proceedings of the Neural Information Processing - 23rd International Conference, 2016

A Deep Neural Network Architecture Using Dimensionality Reduction with Sparse Matrices.
Proceedings of the Neural Information Processing - 23rd International Conference, 2016

2013
A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

High-parallel performance-aware LDPC decoder IP core design for WiMAX.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
DVB-T2 LDPC Decoder with Perfect Conflict Resolution.
IPSJ Trans. Syst. LSI Des. Methodol., 2012

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2011
A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Ultra low power QC-LDPC decoder with high parallelism.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

Generic Permutation Network for QC-LDPC Decoder.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network.
IEICE Trans. Electron., 2010

An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010


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