Satoshi Goto

According to our database1, Satoshi Goto authored at least 332 papers between 1979 and 2022.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 1987, "For contributions to new directions on VLSI CAD research.".

Timeline

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Bibliography

2022
Multi-track Transfer Reinforcement Learning for Power Consumption Management of Building Multi-type Air-Conditioners.
Proceedings of the Engineering Applications of Neural Networks, 2022

2021
Clustering for time-varying relational count data.
Comput. Stat. Data Anal., 2021

Keynote Speech 2: ICT Trend and Future.
Proceedings of the 31st International Conference on Computer Theory and Applications, 2021

2020
Analysis on the Usage of Topic Model with Background Knowledge inside Discussion Activity in Industrial Engineering Context.
Proceedings of the 2020 IEEE International Conference on Smart Internet of Things, 2020

2019
Empirical Study of Multi-party Workshop Facilitation in Strategy Planning Phase for Product Lifecycle Management System.
Proceedings of the Product Lifecycle Management in the Digital Twin Era, 2019

2018
A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC.
IEEE Trans. Circuits Syst. Video Technol., 2018

Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging.
IEEE Trans. Biomed. Circuits Syst., 2018

Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing.
IEICE Trans. Electron., 2018

Lossy Compression for Embedded Computer Vision Systems.
IEEE Access, 2018

Design for IoT Business Modeling Workshop: A Case Study of Collaborative University-Industry Education Program.
Proceedings of the Product Lifecycle Management to Support Industry 4.0, 2018

2017
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC.
IEEE Trans. Multim., 2017

VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications.
IEEE Trans. Circuits Syst. Video Technol., 2017

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design.
IEEE J. Solid State Circuits, 2017

Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor.
IEICE Trans. Electron., 2017

Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Real-Time UHD Background Modelling with Mixed Selection Block Updates.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

100x Evolution of Video Codec Chips.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Past, Present and Future of the Research.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Approximate-DCT-derived measurement matrices for compressed sensing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Measurement-domain intra prediction framework for compressively sensed images.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Preliminary Study on Workshop Facilitation for IoT Innovation as Industry-University Collaboration PLM Program for Small and Medium Sized Enterprises.
Proceedings of the Product Lifecycle Management and the Industry of the Future, 2017

2016
14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Multi-party Interactive Visioneering Workshop for Smart Connected Products in Global Manufacturing Industry Considering PLM.
Proceedings of the Product Lifecycle Management for Digital Transformation of Industries, 2016

Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems.
Proceedings of the 2016 IEEE International Conference on Multimedia & Expo Workshops, 2016

2015
A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Ultra-High-Throughput VLSI Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications.
IEEE Trans. Circuits Syst. Video Technol., 2015

A fast encoder of frame-compatible format based on content similarity for 3D distribution.
Signal Process. Image Commun., 2015

Block-Propagative Background Subtraction System for UHDTV Videos.
IPSJ Trans. Comput. Vis. Appl., 2015

A professional training programme design for global manufacturing strategy: investigations and action project group activities through industry-university cooperation.
Int. J. Bus. Inf. Syst., 2015

High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Low-Power Motion Estimation Processor with 3D Stacked Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Human Detection Method Based on Non-Redundant Gradient Semantic Local Binary Patterns.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Adaptive Block-Propagative Background Subtraction Method for UHDTV Foreground Detection.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

An independent bandwidth reduction device for HEVC VLSI video system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A fixed-complexity HEVC inter mode filtering algorithm based on distribution of IME-FME cost ratio.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec.
IEEE Trans. Multim., 2014

Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC.
J. Vis. Commun. Image Represent., 2014

A 1.59 Gpixel/s Motion Estimation Processor With -211 to +211 Search Range for UHDTV Video Encoder.
IEEE J. Solid State Circuits, 2014

Imaging-Based Rating for Corrosion States of Weathering Steel Using Wavelet Transform and PSO-SVM Techniques.
J. Comput. Civ. Eng., 2014

Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Fast Prediction Unit Selection and Mode Selection for HEVC Intra Prediction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Dynamic Check Message Majority-Logic Decoding Algorithm for Non-binary LDPC Codes.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Real-Time Refinement Method for Foreground Objects Detectors Using Super Fast Resolution-Free Tracking System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Multi-Voltage and Level-Shifter Assignment Driven Floorplanning.
CoRR, 2014

An efficient and accurate approach of circular object detection in color images.
Comput. Electr. Eng., 2014

A low power 720p motion estimation processor with 3D stacked memory.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder.
Proceedings of the Advances in Multimedia Information Processing - PCM 2014, 2014

Low-Complexity Rate-Distortion Optimization Algorithms for HEVC Intra Prediction.
Proceedings of the MultiMedia Modeling - 20th Anniversary International Conference, 2014

A high parallel way for processing IQ/IT part of HEVC decoder based on GPU.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2014

An efficient decoder architecture for cyclic non-binary LDPC codes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Motion compensation architecture for 8K UHDTV HEVC decoder.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2014

Fast SAO estimation algorithm and its VLSI architecture.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

VLSI architecture of HEVC intra prediction for 8K UHDTV applications.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Reducing power consumption of HEVC codec with lossless reference frame recompression.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

A 610 Mbin/s CABAC decoder for H.265/HEVC level 6.1 applications.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

OpenCL based high-quality HEVC motion estimation on GPU.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Non-Redundant Gradient Semantic Local Binary Patterns for pedestrian detection.
Proceedings of the 22nd European Signal Processing Conference, 2014

Live demonstration: FPGA based 3840×2160 video decoding and displaying system.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Retinex based visual identicalness detection for videos corrupted by imaging noise.
Signal Process. Image Commun., 2013

A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

An Integrated Hole-Filling Algorithm for View Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Joint Feature Based Rain Detection and Removal from Videos.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Bidirectional Local Template Patterns: An Effective and Discriminative Feature for Pedestrian Detection.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Content Adaptive Hierarchical Decision of Variable Coding Block Sizes in High Efficiency Video Coding for High Resolution Videos.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

All-Zero Block-Based Optimization for Quadtree-Structured Prediction and Residual Encoding in High Efficiency Video Coding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Hybrid Message-Passing Algorithm and Architecture for Decoding Cyclic Non-binary LDPC Codes.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Correlated Noise Reduction for Electromagnetic Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Examination of a tracking and detection method using compressed domain information.
Proceedings of the 30th Picture Coding Symposium, 2013

High-parallel performance-aware LDPC decoder IP core design for WiMAX.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Multi-scale bidirectional local template patterns for real-time human detection.
Proceedings of the 15th IEEE International Workshop on Multimedia Signal Processing, 2013

A mode filtering algorithm for accelerating HEVC FME.
Proceedings of the 15th IEEE International Workshop on Multimedia Signal Processing, 2013

Delay-driven layer assignment in global routing under multi-tier interconnect structure.
Proceedings of the International Symposium on Physical Design, 2013

Gradient Local Binary Patterns for human detection.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An FPGA-based 4K UHDTV H.264/AVC video decoder.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, 2013

Low-complexity merge candidate decision for fast HEVC encoding.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, 2013

A combined SAO and de-blocking filter architecture for HEVC video decoder.
Proceedings of the IEEE International Conference on Image Processing, 2013

A high-performance CABAC encoder architecture for HEVC and H.264/AVC.
Proceedings of the IEEE International Conference on Image Processing, 2013

Combined hole-filling with spatial and temporal prediction.
Proceedings of the IEEE International Conference on Image Processing, 2013

Lossless embedded compression using multi-mode DPCM & averaging prediction for HEVC-like video codec.
Proceedings of the 21st European Signal Processing Conference, 2013

A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Transform-based fast mode and depth decision algorithm for HEVC intra prediction.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A low-complexity coding scheme for non-binary LDPC code based on IDRB-MLGD algorithm.
Proceedings of the 9th International Conference on Information, 2013

Image segmentation approach for realizing zoomable streaming HEVC video.
Proceedings of the 9th International Conference on Information, 2013

2012
An Advanced Hierarchical Motion Estimation Scheme With Lossless Frame Recompression and Early-Level Termination for Beyond High-Definition Video Coding.
IEEE Trans. Multim., 2012

Hilbert Transform-Based Workload Prediction and Dynamic Frequency Scaling for Power-Efficient Video Encoding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

DVB-T2 LDPC Decoder with Perfect Conflict Resolution.
IPSJ Trans. Syst. LSI Des. Methodol., 2012

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips.
IEICE Trans. Electron., 2012

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Framework of a Contour Based Depth Map Coding Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Encoder-Unconstrained User Interactive Partial Decoding Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Pedestrian Detection Using Gradient Local Binary Patterns.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC.
Proceedings of the Symposium on VLSI Circuits, 2012

Enhanced moving object detection using tracking system for video surveillance purposes.
Proceedings of the 2012 Visual Communications and Image Processing, 2012

A KLT-based approach for occlusion handling in human tracking.
Proceedings of the 2012 Picture Coding Symposium, 2012

Content adaptive prediction unit size decision algorithm for HEVC intra coding.
Proceedings of the 2012 Picture Coding Symposium, 2012

A 18.42 times faster video encoder based on Retinex theory.
Proceedings of the 2012 Picture Coding Symposium, 2012

An Integrated Hole-Filling Algorithm for View Synthesis.
Proceedings of the Advances in Multimedia Information Processing - PCM 2012, 2012

De-blocking Filter Design for HEVC and H.264/AVC.
Proceedings of the Advances in Multimedia Information Processing - PCM 2012, 2012

Motion robust rain detection and removal from videos.
Proceedings of the 14th IEEE International Workshop on Multimedia Signal Processing, 2012

A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Stereo matching with pixel classification and reliable disparity propagation.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

Interlaced asymmetric search range assignment for bidirectional motion estimation.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

An optimized MC interpolation architecture for HEVC.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

Voltage island-driven power optimization for application specific network-on-chip design.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Pedestrian detection based on bidirectional local template patterns.
Proceedings of the 20th European Signal Processing Conference, 2012

Distributed punctured LDPC coding scheme using novel shuffled decoding for MIMO relay channels.
Proceedings of the 20th European Signal Processing Conference, 2012

A 1991 Mpixels/s intra prediction architecture for Super Hi-Vision H.264/AVC encoder.
Proceedings of the 20th European Signal Processing Conference, 2012

Linear optimal one-sided single-detour algorithm for untangling twisted bus.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

An optimization scheme for quadtree-structured prediction and residual encoding in HEVC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

An efficient majority-logic based message-passing algorithm for non-binary LDPC decoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

Envelope detection based workload prediction for partial decoding scheme.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Buffer Planning for IP Placement Using Sliced-LFF.
VLSI Design, 2011

Composite Model-Based DC Dithering for Suppressing Contour Artifacts in Decompressed Video.
IEEE Trans. Image Process., 2011

Encoder adaptable difference detection for low power video compression in surveillance system.
Signal Process. Image Commun., 2011

Efficient motion vector prediction algorithm using pattern matching.
J. Vis. Commun. Image Represent., 2011

The Switching Glitch Power Leakage Model.
J. Softw., 2011

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip.
IEEE J. Solid State Circuits, 2011

Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder.
IEICE Trans. Electron., 2011

Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining.
IEICE Trans. Electron., 2011

Watermarking for HDR Image Robust to Tone Mapping.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder.
IEICE Trans. Electron., 2011

A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC.
IEICE Trans. Electron., 2011

A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Low bit rate overhead based reference modification for error resilient video coding.
IEICE Electron. Express, 2011

Multipath Delay Profile Models for ITS in 700MHz Band.
Proceedings of the 74th IEEE Vehicular Technology Conference, 2011

A fast encoder of frame-compatible format based on content similarity for 3D distribution.
Proceedings of the 2011 IEEE Visual Communications and Image Processing, 2011

Low power parallel surveillance video encoding system based on joint power-speed scheduling.
Proceedings of the 2011 IEEE Visual Communications and Image Processing, 2011

Adaptive raster scan for slice/frame coding.
Proceedings of the 2011 IEEE Visual Communications and Image Processing, 2011

Ultra low power QC-LDPC decoder with high parallelism.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Block-based codebook model with oriented-gradient feature for real-time foreground detection.
Proceedings of the IEEE 13th International Workshop on Multimedia Signal Processing (MMSP 2011), 2011

A Novel Depth-Image Based View Synthesis Scheme for Multiview and 3DTV.
Proceedings of the Advances in Multimedia Modeling, 2011

Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Novel and efficient min cut based voltage assignment in gate level.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Adaptive temporal scalable decoding scheme with temporal and spatial prediction method.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

Bilateral filtering based watermarking for high dynamic range image.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

Object tracking by detection for video surveillance systems based on modified codebook foreground detection and particle filter.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

Region-interior painting in Contour Based Depth map Coding System.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

A Multiple Bits Output Ring-Oscillator Physical Unclonable Function.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

A 98 GMACs/W 32-core vector processor in 65nm CMOS.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Floorplanning driven Network-on-Chip synthesis for 3-D SoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Proposed optimization for AdaBoost-based face detection.
Proceedings of the Third International Conference on Digital Image Processing, 2011

A 16-65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications.
Proceedings of the 19th European Signal Processing Conference, 2011

A fast Intra encoder of frame-compatible format based on content similarity for 3D distribution.
Proceedings of the 19th European Signal Processing Conference, 2011

A 1 Gbin/s CABAC encoder for H.264/AVC.
Proceedings of the 19th European Signal Processing Conference, 2011

A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

Network flow-based simultaneous retiming and slack budgeting for low power design.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

A study on channel polarization and polar coding.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

High-parallel LDPC decoder with power gating design.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Through-Silicon-Via assignment for 3D ICs.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Electromagnetic Analysis Enhancement with Signal Processing Techniques (Poster).
Proceedings of the Information Security and Privacy - 16th Australasian Conference, 2011

2010
High Profile Intra Prediction Architecture for UHD H.264 Decoder.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Accurate Human Detection by Appearance and Motion.
IEICE Trans. Inf. Syst., 2010

Histogram of Template for Pedestrian Detection.
IEICE Trans. Inf. Syst., 2010

Generic Permutation Network for QC-LDPC Decoder.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network.
IEICE Trans. Electron., 2010

A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder.
IEICE Trans. Electron., 2010

Self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder.
IEICE Electron. Express, 2010

Correlation Power Analysis Based on Switching Glitch Model.
Proceedings of the Information Security Applications - 11th International Workshop, 2010

Difference detection based early mode termination for depth map coding in MVC.
Proceedings of the Picture Coding Symposium, 2010

Intra prediction architecture for H.264/AVC QFHD encoder.
Proceedings of the Picture Coding Symposium, 2010

A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding.
Proceedings of the Advances in Multimedia Information Processing - PCM 2010, 2010

Temporal Scalable Decoding Process with Frame Rate Conversion Method for Surveillance Video.
Proceedings of the Advances in Multimedia Information Processing - PCM 2010, 2010

An Efficient Frame Loss Error Concealment Scheme Based on Tentative Projection for H.264/AVC.
Proceedings of the Advances in Multimedia Information Processing - PCM 2010, 2010

Error concealment considering error propagation inside a frame.
Proceedings of the 2010 IEEE International Workshop on Multimedia Signal Processing, 2010

Enhanced Temporal Error Concealment for 1Seg Video Broadcasting.
Proceedings of the Advances in Multimedia Modeling, 2010

Fixed outline multi-bend bus driven floorplanning.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

An adaptive bandwidth reduction scheme for video coding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A lossless frame recompression scheme for reducing DRAM power in video encoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low power surveillance video coding system.
Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010

An advanced hierarchical motion estimation scheme with lossless frame recompression for ultra high definition video coding.
Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010

Multi scale block histogram of template feature for pedestrian detection.
Proceedings of the International Conference on Image Processing, 2010

Hilbert transform based workload estimation for low power surveillance video compression.
Proceedings of the International Conference on Image Processing, 2010

Histogram of template for human detection.
Proceedings of the IEEE International Conference on Acoustics, 2010

A revisit to voltage partitioning problem.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Bus via reduction based on floorplan revising.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A constant rate bandwidth reduction architecture with adaptive compression mode decision for video decoding.
Proceedings of the 18th European Signal Processing Conference, 2010

A novel hardware-friendly self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder.
Proceedings of the 18th European Signal Processing Conference, 2010

Coverage performance of MB-OFDM UWB in-car wireless communication.
Proceedings of the 7th International Symposium on Communication Systems Networks and Digital Signal Processing, 2010

Floorplanning and topology generation for application-specific network-on-chip.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

Complexity reduction algorithm for region-of-interest based H.264 encoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Human tracking system for automatic video surveillance with particle filters.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Motion Estimation Optimization for H.264/AVC Using Source Image Edge Features.
IEEE Trans. Circuits Syst. Video Technol., 2009

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis.
IEEE J. Solid State Circuits, 2009

A Low Bandwidth Integer Motion Estimation Module for MPEG-2 to H.264 Transcoding.
IPSJ Trans. Syst. LSI Des. Methodol., 2009

A High Throughput LDPC Decoder Design Based on Novel Delta-value Message-passing Schedule.
IPSJ Trans. Syst. LSI Des. Methodol., 2009

A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Voltage and Level-Shifter Assignment Driven Floorplanning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

An Ultra-Low Bandwidth Design Method for MPEG-2 to H.264/AVC Transcoding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Integrated interlayer via planning and pin assignment for 3D ICs.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Region-of-interest based dynamical parameter allocation for H.264/AVC encoder.
Proceedings of the 2009 Picture Coding Symposium, 2009

Optical flow based DC surface compensation for artifacts reduction.
Proceedings of the 2009 Picture Coding Symposium, 2009

Region-of-interest based H.264 encoder for videophone with a hardware macroblock level face detector.
Proceedings of the 2009 IEEE International Workshop on Multimedia Signal Processing, 2009

A Fast Hybrid Decision Algorithm for H.264/AVC Intra Prediction Based on Entropy Theory.
Proceedings of the Advances in Multimedia Modeling, 2009

Prioritized Reference Decision for Efficient Motion Vector Coding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Side Match Distortion based Adaptive Error Concealment order for 1Seg Video Broadcasting Application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Pedestrian Detection with an Ensemble of Localized Features.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Parallel HD Encoding on CELL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Buffer Planning for 3D ICs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Block-pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A 136 cycles/MB, luma-chroma parallelized H.264/AVC deblocking filter for QFHD applications.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Composite modeling of optical flow for artifacts reduction.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Motion Detection Based on Background Modeling and Performance Analysis for Outdoor Surveillance.
Proceedings of the International Conference on Computer Modeling and Simulation, 2009

A New DCT-Domain Distortion Model for MB-Level Quality Control.
Proceedings of the International Conference on Computer Modeling and Simulation, 2009

Voltage-island driven floorplanning considering level-shifter positions.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

A high performance LDPC decoder for IEEE802.11n standard.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC.
J. Signal Process. Syst., 2008

Motion Feature and Hadamard Coefficient-Based Fast Multiple Reference Frame Motion Estimation for H.264.
IEEE Trans. Circuits Syst. Video Technol., 2008

Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

An Irregular Search Window Reuse Scheme for MPEG-2 to H.264 Transcoding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems.
IEICE Trans. Electron., 2008

Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Content-Aware Fast Motion Estimation for H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm.
IEICE Trans. Electron., 2008

A High-Speed Design of Montgomery Multiplier.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Adaptive Search Range Algorithms for Variable Block Size Motion Estimation in H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

An Adaptive Spatial Error Concealment for H.264/AVC Video Stream.
Proceedings of the SIGMAP 2008, 2008

Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

VLSI friendly computation reduction scheme in H.264/AVC motion estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Hardware-oriented direction-based fast fractional motion estimation algorithm in H.264/AVC.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Fast motion estimation for H.264/AVC using image edge features.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

A motion vector difference based self-incremental adaptive search range algorithm for variable block size motion estimation.
Proceedings of the International Conference on Image Processing, 2008

Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264.
Proceedings of the 26th International Conference on Computer Design, 2008

A novel fixed-outline floorplanner with zero deadspace for hierarchical design.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

HyMacs: hybrid memory access optimization based on custom-instruction scheduling.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Bandwidth reduction schemes for MPEG-2 to H.264 transcoder design.
Proceedings of the 2008 16th European Signal Processing Conference, 2008

Cache miss reduction through hardware-assisted loop optimization.
Proceedings of the 12th International Conference on CSCW in Design, 2008

Symmetry constraint based on mismatch analysis for analog layout in SOI technology.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

A frequency-based fast block type decision algorithm for intra prediction in H.264/AVC high profile.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A low bandwidth integer motion estimation module for MPEG-2 to H.264 transcoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A block type decision algorithm for H.264/AVC intra prediction based on entropy feature.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
An MRF model-based approach to the detection of rectangular shape objects in color images.
Signal Process., 2007

Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms.
IEICE Trans. Electron., 2007

Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations.
IEICE Trans. Inf. Syst., 2007

Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Periodic Spectrum Transmission for Single-Carrier Transmission Frequency-Domain Equalization.
IEICE Trans. Commun., 2007

Geometrical, Physical and Text/Symbol Analysis Based Approach of Traffic Sign Detection System.
IEICE Trans. Inf. Syst., 2007

Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding.
IEICE Trans. Inf. Syst., 2007

Fast Methods to Estimate Clock Jitter due to Power Supply Noise.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

H.264/AVC Fractional Motion Estimation Engine with Computation Reusing in HDTV1080P Real-Time Encoding Applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

32-Parallel SAD Tree Hardwired Engine for Variable Block Size Motion Estimation in HDTV1080P Real-Time Encoding Application.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

A New Video Encryption Scheme for H.264/AVC.
Proceedings of the Advances in Multimedia Information Processing, 2007

Power-efficient LDPC code decoder architecture.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

An Irregular Search Window Reuse Scheme for Motion Estimation in MPEG-2 to H.264 Transcoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Enhanced Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Motion Vector Prediction Scheme for MPEG-2 to H.264 Transcoding Based on Smoothness of Motion Vector Field.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

Ultra Low-Complexity Fast Variable Block Size Motion Estimation Algorithm in H.264/AVC.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

VLSI Oriented Fast Multiple Reference Frame Motion Estimation Algorithm for H.264/AVC.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for H.264/avc.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

VLSI friendly edge gradient detection based multiple reference frames motion estimation optimization for H.264/AVC.
Proceedings of the 15th European Signal Processing Conference, 2007

2006
A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC.
IEICE Trans. Electron., 2006

A Selective Video Encryption Scheme for MPEG Compression Standard.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Contour-Based Robust Algorithm for Text Detection in Color Images.
IEICE Trans. Inf. Syst., 2006

A Hardware Implementation of a Content-Based Motion Estimation Algorithm for Real-Time MPEG-4 Video Coding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Inter-symbol Interference Suppression Scheme using Periodic Signal Waveform for Fixed-rate COFDM Systems.
Proceedings of the 63rd IEEE Vehicular Technology Conference, 2006

A Fully Automatic Approach of Color Image Edge Detection.
Proceedings of the IEEE International Conference on Systems, 2006

An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC.
Proceedings of the Advances in Visual Computing, Second International Symposium, 2006

System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

High performance VLSI architecture of fractional motion estimation in H.264 for HDTV.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A parallel LSI architecture for LDPC decoder improving message-passing schedule.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An ultra-low complexity motion estimation algorithm and its implementation of specific processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low-Pass Filter Based Vlsi Oriented Variable Block Size Motion Estimation Algorithm for H.264.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

High-throughput decoder for low-density parity-check code.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A New Multiscale Line Detection Approach for Aerial Image with Complex Scene.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Enhanced Partial Distortion Sorting Fast Motion Estimation Algorithm for Low-Power Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Memory-Efficient Accelerating Schedule for LDPC Decoder.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Robust Scalable Video Transmission using Object-Oriented Unequal Loss Protection over Internet.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Novel Hybrid Approach of Color Image Segmentation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A CABAC Encoding Core with Dynamic Pipeline for H.264/AVC Main Profile.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Geometric Primitives Detection in Aerial Image.
Proceedings of the Firth IEEE International Conference on Cognitive Informatics, 2006

A Novel Approach of Rectangular Shape Object Detection in Color Images Based on An MRF Model.
Proceedings of the Firth IEEE International Conference on Cognitive Informatics, 2006

2005
Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving.
IEICE Trans. Inf. Syst., 2005

A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Content-Based Motion Estimation with Extended Temporal-Spatial Analysis.
IEICE Trans. Inf. Syst., 2005

A Highly Parallel Architecture for Deblocking Filter in H.264/AVC.
IEICE Trans. Inf. Syst., 2005

Inter-symbol Interference Suppression Employing Sub-carrier Group Selection for OFDM-TDD Transmit Diversity.
Proceedings of the 2nd IEEE International Symposium on Wireless Communication Systems, 2005

A locally adaptive subsampling algorithm for software based motion estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An accurate and low complexity approach of detecting circular shape objects in still color images.
Proceedings of the 2005 International Conference on Image Processing, 2005

A Robust Algorithm for Text Detection in Color Images.
Proceedings of the Eighth International Conference on Document Analysis and Recognition (ICDAR 2005), 29 August, 2005

Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Reconfigurable adaptive FEC system with interleaving.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

1987
Compaction-Based Custom LSI Layout Design Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1984
Knowledge-Based VLSI Routing System - WIREX.
Proceedings of the International Conference on Fifth Generation Computer Systems, 1984

1983
lambda, an integrated master-slice LSI CAD system.
Integr., 1983

1982
LAMBDA: A quick, low cost layout design system for master-slice LSI s.
Proceedings of the 19th Design Automation Conference, 1982

1979
A two-dimensional placement algorithm for the master slice LSI layout problem.
Proceedings of the 16th Design Automation Conference, 1979


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