Zhixiang Chen

According to our database, Zhixiang Chen authored at least 19 papers between 2010 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding.

Gang He, Dajiang Zhou, Yunsong Li, Zhixiang Chen, Tianruo Zhang, Satoshi Goto

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications.

Gang He, Dajiang Zhou, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS.

Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

High-parallel performance-aware LDPC decoder IP core design for WiMAX.

Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS.

Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS.

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

DVB-T2 LDPC Decoder with Perfect Conflict Resolution.

Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto

IPSJ Trans. Syst. LSI Des. Methodol., 2012

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX.

Xiongxin Zhao, Xiao Peng, Zhixiang Chen, Dajiang Zhou, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC.

Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto

Proceedings of the Symposium on VLSI Circuits, 2012

An efficient majority-logic based message-passing algorithm for non-binary LDPC decoding.

Yichao Lu, Nanfan Qiu, Zhixiang Chen, Satoshi Goto

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip.

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Ultra low power QC-LDPC decoder with high parallelism.

Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering.

Qian Xie, Qian He, Xiao Peng, Ying Cui, Zhixiang Chen, Dajiang Zhou, Satoshi Goto

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS.

Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Dajiang Zhou, Satoshi Goto

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application.

Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Generic Permutation Network for QC-LDPC Decoder.

Xiao Peng, Xiongxin Zhao, Zhixiang Chen, Fumiaki Maehara, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network.

Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Fumiaki Maehara, Satoshi Goto

IEICE Trans. Electron., 2010

An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards.

Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder.

Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Fumiaki Maehara, Satoshi Goto

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010