Xu Zhang

Orcid: 0009-0009-0027-9818

Affiliations:

Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China

According to our database¹, Xu Zhang authored at least 7 papers between 2021 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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Bibliography

2025

DRack: A CXL-Disaggregated Rack Architecture to Boost Inter-Rack Communication.

[BibT_eX]

[DOI]

Proceedings of the 2025 USENIX Annual Technical Conference, 2025

2024

Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., September, 2024

DFabric: Scaling Out Data Parallel Applications with CXL-Ethernet Hybrid Interconnects.

[BibT_eX]

[DOI]

CoRR, 2024

2023

Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Rethinking Design Paradigm of Graph Processing System with a CXL-like Memory Semantic Fabric.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE/ACM International Symposium on Cluster, 2023

2022

GraFF: A Multi-FPGA System with Memory Semantic Fabric for Scalable Graph Processing.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

2021

Asynchronous Memory Access Unit for General Purpose Processors.

[BibT_eX]

[DOI]

CoRR, 2021

Xu Zhang

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