Yisong Chang

Orcid: 0009-0007-3153-2615

According to our database1, Yisong Chang authored at least 24 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
XUNI: Virtual Machine Abstraction for Self-contained and Multi-tenant Cloud FPGAs.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023
Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

REMU: Enabling Cost-Effective Checkpointing and Deterministic Replay in FPGA-based Emulation.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

MARB: Bridge the Semantic Gap between Operating System and Application Memory Access Behavior.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Rethinking Design Paradigm of Graph Processing System with a CXL-like Memory Semantic Fabric.
Proceedings of the 23rd IEEE/ACM International Symposium on Cluster, 2023

2022
GraFF: A Multi-FPGA System with Memory Semantic Fabric for Scalable Graph Processing.
Proceedings of the International Conference on Field-Programmable Technology, 2022

FPL Demo: SERVE: Agile Hardware Development Platform with Cloud IDE and Cloud FPGAs.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Increasing Flexibility of Cloud FPGA Virtualization.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
Teaching Computer System Courses with an Online Large-Scale Method.
Proceedings of the 2021 IEEE International Conference on Engineering, 2021

EdUCAS: An In-house CI/CD Platform with Cloud FPGAs for Agilely Conducting Computer Systems Course Projects.
Proceedings of the ITiCSE '21: Proceedings of the 26th ACM Conference on Innovation and Technology in Computer Science Education V.2, Virtual Event, Germany, June 26, 2021

2019
ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Computer Organization and Design Course with FPGA Cloud.
Proceedings of the 50th ACM Technical Symposium on Computer Science Education, 2019

Engaging Heterogeneous FPGAs in the Cloud.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

ZyCube: An In-House Mini-Cluster for Agilely Developing and Conducting Computer Systems Course Projects.
Proceedings of the ACM Conference on Global Computing Education, 2019

2018
On Retargeting the AI Programming Framework to New Hardwares.
Proceedings of the Network and Parallel Computing, 2018

2017
DoCE: Direct Extension of On-Chip Interconnects over Converged Ethernet for Rack-Scale Memory Sharing.
Proceedings of the first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters, 2017

2016
Titian2: a scalable system-level emulator with all programmability for datacenter servers in cloud computing.
Proceedings of the 9th International Conference on Utility and Cloud Computing, 2016

Co-DIMM: Inter-Socket Data Sharing via a Common DIMM Channel.
Proceedings of the Second International Symposium on Memory Systems, 2016

Extending On-chip Interconnects for rack-level remote resource access.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

sAXI: A High-Efficient Hardware Inter-Node Link in ARM Server for Remote Memory Access.
Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

2015
A modified post-TnL vertex cache for the multi-shader embedded GPUs.
IEICE Electron. Express, 2015

2013
A high performance, area efficient TTA-like vertex shader architecture with optimized floating point arithmetic unit for embedded graphics applications.
Microprocess. Microsystems, 2013

2011
An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unit.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A Novel Architecture for Fast RSA Key Generation Based on RNS.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011


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