Xuanle Ren

Orcid: 0000-0002-8272-1164

According to our database1, Xuanle Ren authored at least 11 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
HEDA: Multi-Attribute Unbounded Aggregation over Homomorphically Encrypted Database.
Proc. VLDB Endow., 2022

An Enclave-based TEE for SE-in-SoC in RISC-V Industry.
CoRR, 2022

2021
Design and Evaluation of Fluctuating Power Logic to Mitigate Power Analysis at the Cell Level.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020
Customizing Trusted AI Accelerators for Efficient Privacy-Preserving Machine Learning.
CoRR, 2020

2019
IC Protection Against JTAG-Based Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
IC protection against JTAG/IJTAG-based attacks
PhD thesis, 2018

Detection of IJTAG attacks using LDPC-based feature reduction and machine learning.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2016
A Learning-Based Approach to Secure JTAG Against Unseen Scan-Based Attacks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Improving accuracy of on-chip diagnosis via incremental learning.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Detection of illegitimate access to JTAG via statistical learning in chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015


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