Shivam Bhasin

According to our database1, Shivam Bhasin authored at least 153 papers between 2009 and 2021.

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Bibliography

2021
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE.
IEEE Trans. Inf. Forensics Secur., 2021

DAPA: Differential Analysis aided Power Attack on (Non-) Linear Feedback Shift Registers.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Attacking and Defending Masked Polynomial Comparison for Lattice-Based Cryptography.
IACR Cryptol. ePrint Arch., 2021

Non-Profiled Side-Channel Attack Based on Deep Learning Using Picture Trace.
IEEE Access, 2021

Time to Leak: Cross-Device Timing Attack On Edge Deep Learning Accelerator.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021

2020
A Framework to Counter Statistical Ineffective Fault Analysis of Block Ciphers Using Domain Transformation and Error Correction.
IEEE Trans. Inf. Forensics Secur., 2020

On Side Channel Vulnerabilities of Bit Permutations in Cryptographic Algorithms.
IEEE Trans. Inf. Forensics Secur., 2020

Persistent Fault Attack in Practice.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Generic Side-channel attacks on CCA-secure lattice-based PKE and KEMs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

SITM: See-In-The-Middle Side-Channel Assisted Middle Round Differential Cryptanalysis on SPN Block Ciphers.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Compact Code-Based Signature for Reconfigurable Devices With Side Channel Resilience.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.
IEEE Trans. Computers, 2020

Branch Prediction Attack on Blinded Scalar Multiplication.
IEEE Trans. Computers, 2020

Towards Designing a Secure RISC-V System-on-Chip: ITUS.
J. Hardw. Syst. Secur., 2020

Neural Network-based Inherently Fault-tolerant Hardware Cryptographic Primitives without Explicit Redundancy Checks.
ACM J. Emerg. Technol. Comput. Syst., 2020

Push For More: On Comparison of Data Augmentation and SMOTE With Optimised Deep Learning Architecture For Side-Channel.
IACR Cryptol. ePrint Arch., 2020

Back To The Basics: Seamless Integration of Side-Channel Pre-processing in Deep Neural Networks.
IACR Cryptol. ePrint Arch., 2020

DAPA: Differential Analysis aided Power Attack on (Non-)Linear Feedback Shift Registers (Extended version).
IACR Cryptol. ePrint Arch., 2020

On Configurable SCA Countermeasures Against Single Trace Attacks for the NTT - A Performance Evaluation Study over Kyber and Dilithium on the ARM Cortex-M4.
IACR Cryptol. ePrint Arch., 2020

Lattice-based Key Sharing Schemes - A Survey.
IACR Cryptol. ePrint Arch., 2020

On Exploiting Message Leakage in (few) NIST PQC Candidates for Practical Message Recovery and Key Recovery Attacks.
IACR Cryptol. ePrint Arch., 2020

Drop by Drop you break the rock - Exploiting generic vulnerabilities in Lattice-based PKE/KEMs using EM-based Physical Attacks.
IACR Cryptol. ePrint Arch., 2020

DNFA: Differential No-Fault Analysis of Bit Permutation Based Ciphers Assisted by Side-Channel.
IACR Cryptol. ePrint Arch., 2020

A Novel Duplication Based Countermeasure To Statistical Ineffective Fault Analysis.
IACR Cryptol. ePrint Arch., 2020

Fault Attacks In Symmetric Key Cryptosystems.
IACR Cryptol. ePrint Arch., 2020

Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks (Extended Version).
IACR Cryptol. ePrint Arch., 2020

SNIFF: Reverse Engineering of Neural Networks with Fault Attacks.
CoRR, 2020

Authentication Protocol for Secure Automotive Systems: Benchmarking Post-Quantum Cryptography.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Practical Reverse Engineering of Secret Sboxes by Side-Channel Analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Learning From A Big Brother - Mimicking Neural Networks in Profiled Side-channel Analysis.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Practical Side-Channel Based Model Extraction Attack on Tree-Based Machine Learning Algorithm.
Proceedings of the Applied Cryptography and Network Security Workshops, 2020

2019
Automatic Characterization of Exploitable Faults: A Machine Learning Approach.
IEEE Trans. Inf. Forensics Secur., 2019

Combining PUF with RLUTs: A Two-party Pay-per-device IP Licensing Scheme on FPGAs.
ACM Trans. Embed. Comput. Syst., 2019

The Curse of Class Imbalance and Conflicting Metrics with Machine Learning for Side-channel Evaluations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Make Some Noise. Unleashing the Power of Convolutional Neural Networks for Profiled Side-channel Analysis.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

CC Meets FIPS: A Hybrid Test Methodology for First Order Side Channel Analysis.
IEEE Trans. Computers, 2019

SCADFA: Combined SCA+DFA Attacks on Block Ciphers with Practical Validations.
IEEE Trans. Computers, 2019

Security is an architectural design constraint.
Microprocess. Microsystems, 2019

Kilroy was here: The First Step Towards Explainability of Neural Networks in Profiled Side-channel Analysis.
IACR Cryptol. ePrint Arch., 2019

Transform-and-Encode: A Countermeasure Framework for Statistical Ineffective Fault Attacks on Block Ciphers.
IACR Cryptol. ePrint Arch., 2019

Generic Side-channel attacks on CCA-secure lattice-based PKE and KEM schemes.
IACR Cryptol. ePrint Arch., 2019

Exploiting Determinism in Lattice-based Signatures - Practical Fault Attacks on pqm4 Implementations of NIST candidates.
IACR Cryptol. ePrint Arch., 2019

Improving Speed of Dilithium's Signing Procedure.
IACR Cryptol. ePrint Arch., 2019

One Fault is All it Needs: Breaking Higher-Order Masking with Persistent Fault Analysis.
IACR Cryptol. ePrint Arch., 2019

SoK : On DFA Vulnerabilities of Substitution-Permutation Networks.
IACR Cryptol. ePrint Arch., 2019

On Misuse of Nonce-Misuse Resistance: Adapting Differential Fault Attacks on (few) CAESAR Winners.
IACR Cryptol. ePrint Arch., 2019

Experimental Evaluation of Deep Neural Network Resistance Against Fault Injection Attacks.
IACR Cryptol. ePrint Arch., 2019

Mind the Portability: A Warriors Guide through Realistic Profiled Side-channel Analysis.
IACR Cryptol. ePrint Arch., 2019

Enhancing Fault Tolerance of Neural Networks for Security-Critical Applications.
CoRR, 2019

CSI NN: Reverse Engineering of Neural Network Architectures Through Electromagnetic Side Channel.
Proceedings of the 28th USENIX Security Symposium, 2019

Lightweight Secure-Boot Architecture for RISC-V System-on-Chip.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

On Comparison of Countermeasures against Statistical Ineffective Fault Attacks.
Proceedings of the 31st International Conference on Microelectronics, 2019

Precise Spatio-Temporal Electromagnetic Fault Injections on Data Transfers.
Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019

Number "Not Used" Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2019

Poster: When Adversary Becomes the Guardian - Towards Side-channel Security With Adversarial Attacks.
Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, 2019

Poster: Recovering the Input of Neural Networks via Single Shot Side-channel Attacks.
Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, 2019

Fluctuating Power Logic: SCA Protection by $V_{DD}$ Randomization at the Cell-level.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018
Toward Threat of Implementation Attacks on Substation Security: Case Study on Fault Detection and Isolation.
IEEE Trans. Ind. Informatics, 2018

Persistent Fault Analysis on Block Ciphers.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA.
J. Hardw. Syst. Secur., 2018

Side-channel Assisted Existential Forgery Attack on Dilithium - A NIST PQC candidate.
IACR Cryptol. ePrint Arch., 2018

Number "Not" Used Once - Key Recovery Fault Attacks on LWE Based Lattice Cryptographic Schemes.
IACR Cryptol. ePrint Arch., 2018

On the Performance of Deep Learning for Side-channel Analysis.
IACR Cryptol. ePrint Arch., 2018

On Side-Channel Vulnerabilities of Bit Permutations: Key Recovery and Reverse Engineering.
IACR Cryptol. ePrint Arch., 2018

CSI Neural Network: Using Side-channels to Recover Your Artificial Neural Network Information.
IACR Cryptol. ePrint Arch., 2018

Protecting Block Ciphers against Differential Fault Attacks without Re-keying (Extended Version).
IACR Cryptol. ePrint Arch., 2018

Online Detection and Reactive Countermeasure for Leakage from BPU Using TVLA.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

On the Performance of Convolutional Neural Networks for Side-Channel Analysis.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2018

PPAP and iPPAP: PLL-Based Protection Against Physical Attacks.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Guessing Your PIN Right: Unlocking Smartphones with Publicly Available Sensor Data.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Feature Selection Methods for Non-Profiled Side-Channel Attacks on ECC.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Protecting block ciphers against differential fault attacks without re-keying.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Breaking Redundancy-Based Countermeasures with Random Faults and Power Side Channel.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

DFARPA: Differential fault attack resistant physical design automation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Practical Fault Attack on Deep Neural Networks.
Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018

On Comparing Side-channel Properties of AES and ChaCha20 on Microcontrollers.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Practical Evaluation of FSE 2016 Customized Encoding Countermeasure.
IACR Trans. Symmetric Cryptol., 2017

Cryptographically Secure Shield for Security IPs Protection.
IEEE Trans. Computers, 2017

Attacks in Reality: the Limits of Concurrent Error Detection Codes Against Laser Fault Injection.
J. Hardw. Syst. Secur., 2017

Extensive Laser Fault Injection Profiling of 65 nm FPGA.
J. Hardw. Syst. Secur., 2017

A study on analyzing side-channel resistant encoding schemes with respect to fault attacks.
J. Cryptogr. Eng., 2017

One Plus One is More than Two: A Practical Combination of Power and Fault Analysis Attacks on PRESENT and PRESENT-like Block Ciphers.
IACR Cryptol. ePrint Arch., 2017

A Practical Fault Attack on ARX-like Ciphers with a Case Study on ChaCha20.
IACR Cryptol. ePrint Arch., 2017

SCADPA: Side-Channel Assisted Differential-Plaintext Attack on Bit Permutation Based Ciphers.
IACR Cryptol. ePrint Arch., 2017

Template Attack on Blinded Scalar Multiplication with Asynchronous perf-ioctl Calls.
IACR Cryptol. ePrint Arch., 2017

There Goes Your PIN: Exploiting Smartphone Sensor Fusion Under Single and Cross User Setting.
IACR Cryptol. ePrint Arch., 2017

Low-cost design of stealthy hardware trojan for bit-level fault attacks on block ciphers.
Sci. China Inf. Sci., 2017

Transistor level SCA-resistant scheme based on fluctuating power logic.
Sci. China Inf. Sci., 2017

An Industrial Outlook on Challenges of Hardware Security in Digital Economy - Extended Abstract -.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2017

Opening pandora's box: Implication of RLUT on secure FPGA applications and IP security.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

An electromagnetic fault injection sensor using Hogge phase-detector.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Side-Channel Attack on STTRAM Based Cache for Cryptographic Application.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Don't fall into a trap: Physical side-channel analysis of ChaCha20-Poly1305.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

An FPGA-compatible PLL-based sensor against fault injection attack.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A systematic security analysis of real-time cyber-physical systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Improved low-entropy masking scheme for LED with mitigation against correlation-enhanced collision attacks.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Method taking into account process dispersion to detect hardware Trojan Horse by side-channel analysis.
J. Cryptogr. Eng., 2016

What Lies Ahead: Extending TVLA Testing Methodology Towards Success Rate.
IACR Cryptol. ePrint Arch., 2016

A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version).
IACR Cryptol. ePrint Arch., 2016

Mistakes Are Proof That You Are Trying: On Verifying Software Encoding Schemes' Resistance to Fault Injection Attacks.
IACR Cryptol. ePrint Arch., 2016

Time-Frequency Analysis for Second-Order Attacks.
IACR Cryptol. ePrint Arch., 2016

Comprehensive Laser Sensitivity Profiling and Data Register Bit-Flips for Cryptographic Fault Attacks in 65 Nm FPGA.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Cheap and Cheerful: A Low-Cost Digital Sensor for Detecting Laser Fault Injection Attacks.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Fault Injection Attacks: Attack Methodologies, Injection Techniques and Protection Mechanisms - A Tutorial.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Attack sensing against EM leakage and injection.
Proceedings of the International SoC Design Conference, 2016

The other side of the coin: Analyzing software encoding schemes against fault injection attacks.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection.
Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016

PLL to the rescue: a novel EM fault countermeasure.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Does it sound as it claims: a detailed side-channel security analysis of QuadSeal countermeasure.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Bypassing Parity Protected Cryptography using Laser Fault Injection in Cyber-Physical System.
Proceedings of the 2nd ACM International Workshop on Cyber-Physical System Security, 2016

Supervised and unsupervised machine learning for side-channel based Trojan detection.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Exploiting FPGA Block Memories for Protected Cryptographic Implementations.
ACM Trans. Reconfigurable Technol. Syst., 2015

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis.
IET Inf. Secur., 2015

Reconfigurable LUT: Boon or Bane for Secure Applications.
IACR Cryptol. ePrint Arch., 2015

Reconfigurable LUT: A Double Edged Sword for Security-Critical Applications.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2015

Challenges in designing trustworthy cryptographic co-processors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A survey on hardware trojan detection techniques.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Support vector regression: exploiting machine learning techniques for leakage modeling.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

From theory to practice of private circuit: A cautionary note.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Fault attacks, injection techniques and tools for simulation.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Integrated Sensor: A Backdoor for Hardware Trojan Insertions?
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Hardware trojan detection by delay and electromagnetic measurements.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.
IEICE Trans. Electron., 2014

Hardware Trojan Horses in Cryptographic IP Cores.
IACR Cryptol. ePrint Arch., 2014

Side-Channel Leakage and Trace Compression using Normalized Inter-Class Variance.
IACR Cryptol. ePrint Arch., 2014

Analysis and Improvements of the DPA Contest v4 Implementation.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2014

Side-channel leakage on silicon substrate of CMOS cryptographic chip.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

A look into SIMON from a side-channel perspective.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology.
Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems, 2014

Encoding the state of integrated circuits: a proactive and reactive protection against hardware Trojans horses.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

DRECON: DPA Resistant Encryption by Construction.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2014, 2014

2013
From cryptography to hardware: analyzing and protecting embedded Xilinx BRAM for cryptographic applications.
J. Cryptogr. Eng., 2013

NICV: Normalized Inter-Class Variance for Detection of Side-Channel Leakage.
IACR Cryptol. ePrint Arch., 2013

Theory of masking with codewords in hardware: low-weight <i>d</i>th-order correlation-immune Boolean functions.
IACR Cryptol. ePrint Arch., 2013

A low-entropy first-degree secure provable masking scheme for resource-constrained devices.
Proceedings of the Workshop on Embedded Systems Security, 2013

2012
From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Towards Different Flavors of Combined Side Channel Attacks.
Proceedings of the Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27, 2012

2011
Logic-Level Countermeasures to Secure FPGA based Designs. (Contremesures au niveau logique pour sécuriser les architectures de crypto-processeurs dans un FPGA).
PhD thesis, 2011

Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks.
IET Inf. Secur., 2011

Efficient Dual-Rail Implementations in FPGA Using Block RAMs.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Embedded systems security: An evaluation methodology against Side Channel Attacks.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2010
Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation.
Proceedings of the Design, Automation and Test in Europe, 2010

Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks.
Proceedings of the Topics in Cryptology, 2010

Countering early evaluation: an approach towards robust dual-rail precharge logic.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

2009
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

WDDL is Protected against Setup Time Violation Attacks.
Proceedings of the Sixth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2009


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