COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.

[BibT_eX]

[DOI]

Haozhe Zhu

Bo Jiao

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

184QPS/W 64Mb/mm<sup>2</sup>3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022

Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network.

[BibT_eX]

[DOI]

Meng-Fan Marvin Chang

Tianchan Guan

Xin Si

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Area Efficient Pattern Representation of Binary Neural Networks on RRAM.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2021

MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing.

[BibT_eX]

[DOI]

CoRR, 2021

2020

iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Advanced Computer Architecture - 13th Conference, 2020

2019

GraphQ: Scalable PIM-Based Graph Processing.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018

SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric.

[BibT_eX]

[DOI]

IEEE Micro, 2017

FlashStorageSim: Performance Modeling for SSD Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

DRISA: a DRAM-based reconfigurable in-situ accelerator.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2015

Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2015

Overcoming the challenges of crossbar resistive memory architectures.

[BibT_eX]

[DOI]

Cong Xu

Dimin Niu

Naveen Muralimanohar

Rajeev Balasubramonian

Tao Zhang

Shimeng Yu

Yuan Xie

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014

SBAC: a statistics based cache bypassing method for asymmetric-access caches.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Architecting 3D vertical resistive memory for next-generation storage systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Reliability-aware cross-point resistive memory design.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Low power multi-level-cell resistive memory design with incomplete data mapping.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Understanding the trade-offs in multi-level cell ReRAM memory design.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Low-Power Design of Emerging Memory Technologies.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Design trade-offs for high density cross-point resistive memory.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Low power memristor-based ReRAM design with Error Correcting Code.

[BibT_eX]

[DOI]

Dimin Niu

Yang Xiao

Yuan Xie

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

F<sup>2</sup>BFLY: an on-chip free-space optical network with wavelength-switching.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Energy-efficient multi-level cell phase-change memory system with data encoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A frequent-value based PRAM memory architecture.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Low-power dual-element memristor based memory design.

[BibT_eX]

[DOI]

Dimin Niu

Yiran Chen

Yuan Xie

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis.

[BibT_eX]

[DOI]

Yibo Chen

Dimin Niu

Yuan Xie

Krishnendu Chakrabarty

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Energy- and endurance-aware design of phase change memory caches.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Impact of process variations on emerging memristor.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Energy and performance driven circuit design for emerging phase-change memory.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Dimin Niu

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