Dimin Niu

According to our database1, Dimin Niu authored at least 30 papers between 2010 and 2018.

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Bibliography

2018
SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric.
IEEE Micro, 2017

FlashStorageSim: Performance Modeling for SSD Architectures.
Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

DRISA: a DRAM-based reconfigurable in-situ accelerator.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2016
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.
ACM Trans. Design Autom. Electr. Syst., 2015

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.
IEEE Trans. Multi-Scale Computing Systems, 2015

Overcoming the challenges of crossbar resistive memory architectures.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
SBAC: a statistics based cache bypassing method for asymmetric-access caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Architecting 3D vertical resistive memory for next-generation storage systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Reliability-aware cross-point resistive memory design.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Low power multi-level-cell resistive memory design with incomplete data mapping.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Understanding the trade-offs in multi-level cell ReRAM memory design.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Low-Power Design of Emerging Memory Technologies.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Design trade-offs for high density cross-point resistive memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Low power memristor-based ReRAM design with Error Correcting Code.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
F2BFLY: an on-chip free-space optical network with wavelength-switching.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Energy-efficient multi-level cell phase-change memory system with data encoding.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A frequent-value based PRAM memory architecture.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Low-power dual-element memristor based memory design.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Energy- and endurance-aware design of phase change memory caches.
Proceedings of the Design, Automation and Test in Europe, 2010

Impact of process variations on emerging memristor.
Proceedings of the 47th Design Automation Conference, 2010

Energy and performance driven circuit design for emerging phase-change memory.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010


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