Ya Jun Yu

According to our database1, Ya Jun Yu authored at least 60 papers between 2000 and 2017.

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Bibliography

2017
Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Design of Low-Power Multiplierless Linear-Phase FIR Filters.
IEEE Access, 2017

Investigation on power consumption of product accumulation block for multiplierless FIR filters.
Proceedings of the 22nd International Conference on Digital Signal Processing, 2017

2016
Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters.
IEEE Trans. on Circuits and Systems, 2016

Power Oriented Design of Linear Phase FIR Filters.
Journal of Circuits, Systems, and Computers, 2016

Improved orthogonal frequency division multiplexing with generalised index modulation.
IET Communications, 2016

Greedy Algorithm for the Design of Linear-Phase FIR Filters with Sparse Coefficients.
CSSP, 2016

Investigation on driver stress utilizing ECG signals with on-board navigation systems in use.
Proceedings of the 14th International Conference on Control, 2016

2015
Generalization of Orthogonal Frequency Division Multiplexing With Index Modulation.
IEEE Trans. Wireless Communications, 2015

Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters.
IEEE Trans. on Circuits and Systems, 2015

New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications.
IEEE Trans. on Circuits and Systems, 2015

Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications.
IEEE Trans. on Circuits and Systems, 2015

Design of high-speed multiplierless linear-phase FIR filters.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Area-time efficient realization of multiple constant multiplication.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fine-grained pipelining for multiple constant multiplications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An efficient FIR filtering technique for processing non-uniformly sampled signal.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

2014
Bit-Level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique.
IEEE Trans. on Circuits and Systems, 2014

Improved Filter Bank Approach for the Design of Variable Bandedge and Fractional Delay Filters.
IEEE Trans. on Circuits and Systems, 2014

A polynomial-time algorithm for the design of multiplierless linear-phase FIR filters with low hardware cost.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

High-speed multiplier block design based on bit-level critical path optimization.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Orthogonal frequency division multiplexing with generalized index modulation.
Proceedings of the IEEE Global Communications Conference, 2014

2013
Investigation on the Optimization Criteria for the Design of Variable Fractional Delay Filters.
IEEE Trans. on Circuits and Systems, 2013

Single-Stage and Cascade Design of High Order Multiplierless Linear Phase FIR Filters Using Genetic Algorithm.
IEEE Trans. on Circuits and Systems, 2013

Sparse FIR filter design based on Genetic Algorithm.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Mixed-Radix Fast Filter Bank Approach for the Design of Variable Digital Filters With Simultaneously Tunable Bandedge and Fractional Delay.
IEEE Trans. Signal Processing, 2012

Fixed-Point Analysis and Parameter Selections of MSR-CORDIC With Applications to FFT Designs.
IEEE Trans. Signal Processing, 2012

Design of high order and wide coefficient wordlength multiplierless FIR filters with low hardware cost using genetic algorithm.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Design of Discrete-Valued Linear Phase FIR Filters in Cascade Form.
IEEE Trans. on Circuits and Systems, 2011

Design of Linear Phase FIR Filters With High Probability of Achieving Minimum Number of Adders.
IEEE Trans. on Circuits and Systems, 2011

Implementation of Linear-Phase FIR Filters for a Rational Sampling-Rate Conversion Utilizing the Coefficient Symmetry.
IEEE Trans. on Circuits and Systems, 2011

Design of variable bandedge FIR filters with extremely large bandedge variation range.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Switching activity analysis and power estimation for multiple constant multiplier block of FIR filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Implementation of Linear-Phase FIR Nearly Perfect Reconstruction Cosine-Modulated Filterbanks Utilizing the Coefficient Symmetry.
IEEE Trans. on Circuits and Systems, 2010

Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space.
CSSP, 2010

Guest Editorial: Low-Power Digital Filter Design Techniques and Their Applications.
CSSP, 2010

Polynomial implementation structure for lagrange-type variable fractional delay filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An adaptive body-bias low voltage low power LC VCO.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low-complexity linear phase fir filters in cascade form.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Low-Complexity Design of Variable Bandedge Linear Phase FIR Filters With Sharp Transition Band.
IEEE Trans. Signal Processing, 2009

Design of Extrapolated Impulse Response FIR Filters With Residual Compensation in Subexpression Space.
IEEE Trans. on Circuits and Systems, 2009

On the Complexity Reduction of Polyphase Linear Phase FIR Filters with Symmetric Coefficient Implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Subexpression encoded extrapolated impulse response FIR filter with perfect residual compensation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms.
IEEE Trans. Signal Processing, 2007

FRM-Based FIR Filters With Optimum Finite Word-Length Performance.
IEEE Trans. Signal Processing, 2007

Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming.
IEEE Trans. on Circuits and Systems, 2007

FRM-Based FIR Filters with Minimum Coefficient Sensitivities.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Roundoff Noise Analysis for FSK Signals in White Noise Represented as Signed Power-of-Two Numbers.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
An efficient implementation of linear-phase FIR filters for a rational sampling rate conversion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Roundoff noise analysis of signals represented using signed power-of-two terms.
Proceedings of the 14th European Signal Processing Conference, 2006

2005
Synthesis of very sharp Hilbert transformer using the frequency-response masking technique.
IEEE Trans. Signal Processing, 2005

Optimum masking levels and coefficient sparseness for Hilbert transformers and half-band filters designed using the frequency-response masking technique.
IEEE Trans. on Circuits and Systems, 2005

Extrapolated impulse response filter and its application in the synthesis of digital filters using the frequency-response masking technique.
Signal Processing, 2005

Signed power-of-two allocation scheme for the design of lattice orthogonal filter banks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Frequency-response-masking technique incorporating extrapolated impulse response band-edge shaping filter.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An efficient algorithm for the optimization of FIR filters synthesized using the multistage frequency-response masking approach.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
An iterative method for optimizing FIR filters synthesized using the two-stage frequency-response masking technique.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Design of discrete-coefficient FIR filters on loosely connected parallel machines.
IEEE Trans. Signal Processing, 2002

FRM based FIR filter design - the WLS approach.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
FPGA implementation of digital filters synthesized using the frequency-response masking technique.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A successive reoptimization approach for the design of discrete coefficient perfect reconstruction lattice filter bank.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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