Xin Lou

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

Ray Reordering for Hardware-Accelerated Neural Volume Rendering.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., November, 2024

RAW Images-Based Motion-Assisted Object Detection Accelerator Using Deformable Parts Models Features on 1080p Videos.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

Multifunctional Optical Tomography System With High-Fidelity Surface Extraction Based on a Single Programmable Scanner and Unified Pinhole Modeling.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Eng., April, 2024

FPGA Accelerator for Human Activity Recognition Based on Radar.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

A Multi-scale Block PatchMatch-based Unified Algorithm for Efficient 6-D Vision Processing.

[BibT_eX]

[DOI]

Hongyu Wang

Xiangyu Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Content-Aware Radiance Fields: Aligning Model Complexity with Scene Intricacy Through Learned Bitwidth Quantization.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2024, 2024

ZeroTetris: A Spacial Feature Similarity-based Sparse MLP Engine for Neural Volume Rendering.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

A 0.59μJ/pixel High-throughput Energy-efficient Neural Volume Rendering Accelerator on FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

An FPGA Accelerator for 3D Cone-beam Sparse-view Computed Tomography Reconstruction.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

Analysis and Design of Precision-Scalable Computation Array for Efficient Neural Radiance Field Rendering.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

Low-Power Reconfigurable FIR Filter Design Based on Common Operation Sharing.

[BibT_eX]

[DOI]

Ling Zhang

Chaolin Rao

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

An Efficient Frequency Domain Vision Pipeline From RAW Images to Backend Tasks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Image Frequency Separation Residual Network for End-to-end RAW to RGB Mapping.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

Design of FRM-Based Nonuniform Filter Bank With Reduced Effective Wordlength for Hearing Aids.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., December, 2022

ICARUS: A Specialized Architecture for Neural Radiance Fields Rendering.

[BibT_eX]

[DOI]

ACM Trans. Graph., 2022

A Raw Image-Based End-to-End Object Detection Accelerator Using HOG Features.

[BibT_eX]

[DOI]

Xiangyu Zhang

Ling Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Block PatchMatch-Based Energy-Resource Efficient Stereo Matching Processor on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Reconfigurable Nonuniform Filter Bank for Hearing Aid Systems.

[BibT_eX]

[DOI]

Tong Ma

Ying Wei

IEEE ACM Trans. Audio Speech Lang. Process., 2022

Multi-Level Time-Frequency Bins Selection for Direction of Arrival Estimation Using a Single Acoustic Vector Sensor.

[BibT_eX]

[DOI]

IEEE ACM Trans. Audio Speech Lang. Process., 2022

Ring and Radius Sampling Based Phasor Field Diffraction Algorithm for Non-Line-of-Sight Reconstruction.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., 2022

Radar-Based Human Activity Recognition With 1-D Dense Attention Network.

[BibT_eX]

[DOI]

Guoji Lai

IEEE Geosci. Remote. Sens. Lett., 2022

ICARUS: A Lightweight Neural Plenoptic Rendering Architecture.

[BibT_eX]

[DOI]

CoRR, 2022

An RRAM-based Neural Radiance Field Processor.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

An End-to-end Computer Vision System Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Learned Smartphone ISP on Mobile GPUs with Deep Learning, Mobile AI & AIM 2022 Challenge: Report.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2022 Workshops, 2022

A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

FPGA Accelerator for Radar-Based Human Activity Recognition.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Gradient-Based Feature Extraction From Raw Bayer Pattern Images.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2021

Lightweight Deep Learning Model in Mobile-Edge Computing for Radar-Based Human Activity Recognition.

[BibT_eX]

[DOI]

Jianping Zhu

IEEE Internet Things J., 2021

A Low-Complexity End-to-End Stereo Matching Pipeline From Raw Bayer Pattern Images to Disparity Maps.

[BibT_eX]

[DOI]

Shengyu Gao

Hongyu Wang

IEEE Access, 2021

Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Multi-Scale Slanted O(1) Stereo Matching Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Stereo Point Cloud Refinement for 3D Object Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

Robust Multi-Source Direction of Arrival Estimation Using a Single Acoustic Vector Sensor.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

Motion Assisted Video-based Stereo Matching.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020

Histogram of Oriented Gradients Feature Extraction From Raw Bayer Pattern Images.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Cascaded Form Sparse FIR Filter Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Histogram of Oriented Gradients Feature Extraction Without Normalization.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019

Design of Sparse FIR Filters With Reduced Effective Length.

[BibT_eX]

[DOI]

Wangqian Chen

Mo Huang

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018

K-SVD Based Denoising Algorithm for DoFP Polarization Image Sensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2<sup>m</sup>) Based on Irreducible All-One Polynomials.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Novel Structure for Area-Efficient Implementation of FIR Filters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Design of Low-Power Multiplierless Linear-Phase FIR Filters.

[BibT_eX]

[DOI]

Wen Bin Ye

IEEE Access, 2017

A passively compensated capacitive sensor readout with biased varactor temperature compensation and temperature coherent quantization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Investigation on power consumption of product accumulation block for multiplierless FIR filters.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Digital Signal Processing, 2017

Low complexity and low power multiplierless FIR filter implementation.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015

New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Design of high-speed multiplierless linear-phase FIR filters.

[BibT_eX]

[DOI]

Wen Bin Ye

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fine-grained pipelining for multiple constant multiplications.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

High-speed multiplier block design based on bit-level critical path optimization.

[BibT_eX]

[DOI]