Yang Zhao
Affiliations:- Duke University, Department of Electrical and Computer Engineering, Durham, NC, USA
- Tsinghua University, Department of Computer Science, Beijing, China (former)
According to our database1,
Yang Zhao
authored at least 22 papers
between 2006 and 2012.
Collaborative distances:
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Bibliography
2012
Optimization Techniques for the Synchronization of Concurrent Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Simultaneous Optimization of Droplet Routing and Control-Pin Mapping to Electrodes in Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
J. Electron. Test., 2012
Springer, ISBN: 978-1-4614-0369-2, 2012
2011
Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
J. Electron. Test., 2011
Co-optimization of droplet routing and pin assignment in disposable digital microfluidic biochips.
Proceedings of the 2011 International Symposium on Physical Design, 2011
2010
Digital Microfluidic Logic Gates and Their Application to Built-in Self-Test of Lab-on-Chip.
IEEE Trans. Biomed. Circuits Syst., 2010
Integrated control-path design and error recovery in the synthesis of digital microfluidic lab-on-chip.
ACM J. Emerg. Technol. Comput. Syst., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
Int. J. Parallel Program., 2009
2008
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the Nano-Net - Third International ICST Conference, 2008
Built-in Self-Test and Fault Diagnosis for Lab-on-Chip Using Digital Microfluidic Logic Gates.
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
2007
Fast and effective fault simulation for path delay faults based on selected testable paths.
Proceedings of the 2007 IEEE International Test Conference, 2007
2006
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture.
Proceedings of the 15th Asian Test Symposium, 2006