Hiroki Morimura

According to our database1, Hiroki Morimura authored at least 19 papers between 1996 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Analysis and Experimental Study of Magnetic-Field Amplification by a Double Coil.
IEEE Trans. Industrial Electronics, 2017

Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier.
IEICE Transactions, 2017

2016
56-Level programmable voltage detector in steps of 50mV for battery management.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
An 8-mode reconfigurable sensor-independent readout circuit for trillion sensors era.
Proceedings of the Tenth IEEE International Conference on Intelligent Sensors, 2015

248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting.
Proceedings of the ESSCIRC Conference 2015, 2015

Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit.
Proceedings of the European Conference on Circuit Theory and Design, 2015

A Wide Frequency PLL-less Clock Generator with Fast Intermittent Operation for Low-Power Wearable Medical Applications.
Proceedings of the 21st Asia-Pacific Conference on Communications, 2015

2014
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.
IEEE Trans. VLSI Syst., 2014

Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting.
IEICE Electronic Express, 2014

2012
1-cm3 event-driven wireless sensor nodes.
Proceedings of the IEEE International Conference on Communication Systems, 2012

2010
Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs.
J. Solid-State Circuits, 2010

Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
A Fingerprint Sensor with Impedance Sensing for Fraud Detection.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI.
IEICE Transactions, 2007

2006
Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier.
IEICE Transactions, 2006

2005
Pixel-Parallel Image-Matching Circuit Schemes for a Single-Chip Fingerprint Sensor and Identifier.
IEICE Transactions, 2005

2002
A Fingerprint Verification Algorithm Using the Differential Matching Rate.
Proceedings of the 16th International Conference on Pattern Recognition, 2002

1999
A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1996
A 1-V 1-Mb SRAM for portable equipment.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996


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