Hiroki Morimura

According to our database1, Hiroki Morimura authored at least 28 papers between 1996 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2017
Analysis and Experimental Study of Magnetic-Field Amplification by a Double Coil.
IEEE Trans. Ind. Electron., 2017

Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier.
IEICE Trans. Electron., 2017

2016
56-Level programmable voltage detector in steps of 50mV for battery management.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
An 8-mode reconfigurable sensor-independent readout circuit for trillion sensors era.
Proceedings of the Tenth IEEE International Conference on Intelligent Sensors, 2015

248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting.
Proceedings of the ESSCIRC Conference 2015, 2015

Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit.
Proceedings of the European Conference on Circuit Theory and Design, 2015

A Wide Frequency PLL-less Clock Generator with Fast Intermittent Operation for Low-Power Wearable Medical Applications.
Proceedings of the 21st Asia-Pacific Conference on Communications, 2015

2014
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting.
IEICE Electron. Express, 2014

2012
Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

1-cm<sup>3</sup> event-driven wireless sensor nodes.
Proceedings of the IEEE International Conference on Communication Systems, 2012

2010
Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs.
IEEE J. Solid State Circuits, 2010

Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
A Fingerprint Sensor with Impedance Sensing for Fraud Detection.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI.
IEICE Trans. Electron., 2007

2006
Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier.
IEICE Trans. Electron., 2006

2005
Pixel-Parallel Image-Matching Circuit Schemes for a Single-Chip Fingerprint Sensor and Identifier.
IEICE Trans. Electron., 2005

2002
A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs.
IEEE J. Solid State Circuits, 2002

A Fingerprint Verification Algorithm Using the Differential Matching Rate.
Proceedings of the 16th International Conference on Pattern Recognition, 2002

A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000
1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs.
IEEE J. Solid State Circuits, 2000

A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors.
IEEE J. Solid State Circuits, 2000

1999
A single-chip fingerprint sensor and identifier.
IEEE J. Solid State Circuits, 1999

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers.
IEEE J. Solid State Circuits, 1999

A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1998
A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's.
IEEE J. Solid State Circuits, 1998

1996
A 1-V 1-Mb SRAM for portable equipment.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996


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