Masafumi Nogawa

According to our database, Masafumi Nogawa authored at least 13 papers between 1994 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.

Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015

A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking.

Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters.

Shinsuke Nakano, Hiroaki Katsurai, Minoru Togashi, Hiroshi Koizumi, Masafumi Nogawa

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Small and Low-Cost Dual-Rate Optical Triplexer for OLT Transceivers in 10G/1G Co-existing 10G-EPON Systems.

Atsushi Kanda, Akira Ohki, Takeshi Kurosaki, Hiroaki Sanjoh, Kota Asaka, Ryoko Yoshimura, Toshio Ito, Makoto Nakamura, Masafumi Nogawa, Yusuke Ohtomo, Mikio Yoneyama

IEICE Trans. Electron., 2013

Session 7 overview: Optical transceivers and silicon photonics.

Ichiro Fujimori, Masafumi Nogawa

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

F3: Emerging technologies for wireline communication.

Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 10Gb/s burst-mode laser diode driver for burst-by-burst power saving.

Hiroshi Koizumi, Minoru Togashi, Masafumi Nogawa, Yusuke Ohtomo

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2008

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs.

Yusuke Ohtomo, Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru Togashi, Kiyomi Kumozaki

IEICE Trans. Electron., 2008

A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI.

Yusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa

IEICE Trans. Electron., 2008

2006

A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS.

Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa

IEEE J. Solid State Circuits, 2006

A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOS.

Masafumi Nogawa, Yusuke Ohtomo, Shunji Kimura, Kazuyoshi Nishimura, Tomoaki Kawamura, Minoru Togashi

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

1998

A data-transition look-ahead DFF circuit for statistical reduction in power consumption.

Masafumi Nogawa, Yusuke Ohtomo

IEEE J. Solid State Circuits, 1998

1994

BiCMOS circuit technology for a 704 MHz ATM switch LSI.

Yusuke Ohtomo, Sadayuki Yasuda, Minoru Togashi, Massyuki Ino, Yasuyuki Tanabe, Jun-ichi Inoue, Masafumi Nogawa, Sshigeki Hino

IEEE J. Solid State Circuits, May, 1994