Yechen Tian

According to our database, Yechen Tian authored at least 6 papers in 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A 5-18-GHz Reconfigurable Quadrature Receiver With Enhanced I-Q Isolation and 100-500-MHz Baseband Bandwidth.

Junyan Bi, Hao Xu, Tenghao Zou, Yaxin Zeng, Yechen Tian, Weitao He, Junjie Gu, Ziyang Jiao, Shubin Liu, Zhangming Zhu, Na Yan

IEEE J. Solid State Circuits, August, 2025

Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency.

Shuai Liu, Yechen Tian, Congyang Sun, Guoyu Li, Hao Xu, Na Yan

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025

Design and Analysis of a 26-32-GHz 6-bit Passive Vector Modulation Phase Shifter for CMOS Bidirectional Transceiver.

Yechen Tian, Yutong Zhang, Junjie Gu, Hao Xu, Weitian Liu, Rui Yin, Zongming Duan, Hao Gao, Na Yan

IEEE Trans. Very Large Scale Integr. Syst., March, 2025

A 2 MHz-BW 80.6 dB-SNDR 95.9 dB-SFDR 2nd-order noise-shaping SAR using open-loop Gm-R amplifier.

Hao Xu, Congyang Sun, Shuai Liu, Guoyu Li, Yechen Tian, Na Yan

Microelectron. J., 2025

A 12-bit 2GS/s current-steering DAC with 27 mW power consumption in 28 nm CMOS.

Beiqi Duan, Junyan Bi, Hao Xu, Guoyu Li, Yechen Tian, Na Yan

Microelectron. J., 2025

7.10 An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS.

Yechen Tian, Junjie Gu, Weitao He, Shuai Liu, Hao Xu, Na Yan

Proceedings of the IEEE International Solid-State Circuits Conference, 2025