Yenai Ma

Orcid: 0000-0002-6156-4999

According to our database1, Yenai Ma authored at least 10 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Cross-layer design of thermally-aware 2.5D systems
PhD thesis, 2020

Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

MGPU-TSM: A Multi-GPU System with Truly Shared Memory.
CoRR, 2020

HALCONE : A Hardware-Level Timestamp-based Cache Coherence Scheme for Multi-GPU systems.
CoRR, 2020

2018
A cross-layer methodology for design and optimization of networks in 2.5D systems.
Proceedings of the International Conference on Computer-Aided Design, 2018

Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2016
UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs.
ACM Trans. Archit. Code Optim., 2016

Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Asymmetric NoC Architectures for GPU Systems.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015


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