Andrew B. Kahng

Orcid: 0000-0002-4490-5018

Affiliations:
  • University of California, San Diego, USA


According to our database1, Andrew B. Kahng authored at least 482 papers between 1989 and 2024.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2012, "For contributions to physical design automation and to design for manufacturability of microelectronic systems.".

IEEE Fellow

IEEE Fellow 2010, "For contributions to the design for manufacturability of integrated circuits, and the technology roadmap of semiconductors".

Timeline

Legend:

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Links

Online presence:

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Bibliography

2024
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route.
ACM Trans. Design Autom. Electr. Syst., January, 2024

NN-Steiner: A Mixed Neural-Algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.
ACM Trans. Design Autom. Electr. Syst., July, 2023

Machine Learning for CAD/EDA: The Road Ahead.
IEEE Des. Test, February, 2023

An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators.
CoRR, 2023

Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations.
CoRR, 2023

K-SpecPart: A Supervised Spectral Framework for Multi-Way Hypergraph Partitioning Solution Improvement.
CoRR, 2023

Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks.
CoRR, 2023

Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration.
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023

The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

An Effective Cost-Skew Tradeoff Heuristic for VLSI Global Routing.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Assessment of Reinforcement Learning for Macro Placement.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022
TritonRoute-WXL: The Open-Source Router With Integrated DRC Engine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

RosettaStone: Connecting the Past, Present, and Future of Physical Design Research.
IEEE Des. Test, 2022

Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Leveling Up: A Trajectory of OpenROAD, TILOS and Beyond.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

A Mixed Open-Source and Proprietary EDA Commons for Education and Prototyping.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

IEEE CEDA DATC: Expanding Research Foundations for IC Physical Design and ML-Enabled EDA.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

AI/ML, Optimization and EDA in the TILOS AI Research Institute.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2021

TritonRoute: The Open-Source Detailed Router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Advancing Placement.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

METRICS2.1 and Flow Tuning in the IEEE CEDA Robust Design Flow and OpenROAD ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Heuristic Methods for Fine-Grain Exploitation of FDSOI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

On the superiority of modularity-based clustering for determining placement-relevant clusters.
Integr., 2020

Tutorial: Open-Source EDA and Machine Learning for IC Design: A Live Update.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Open-Source EDA: If We Build It, Who Will Come?
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Optimal bounded-skew steiner trees to minimize maximum <i>k</i>-active dynamic power.
Proceedings of the SLIP '20: System-Level Interconnect, 2020

Revisiting inherent noise floors for interconnect prediction.
Proceedings of the SLIP '20: System-Level Interconnect, 2020

MLCAD Today and Tomorrow: Learning, Optimization and Scaling.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

The Tao of PAO: Anatomy of a Pin Access Oracle for Detailed Routing.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Enhancing sensitivity-based power reduction for an industry IC design context.
Integr., 2019

Looking Into the Mirror of Open Source: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop.
Proceedings of the International Conference on Computer-Aided Design, 2019

DATC RDF-2019: Towards a Complete Academic Reference Design Flow.
Proceedings of the International Conference on Computer-Aided Design, 2019

"Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Diffusion break-aware leakage power optimization and detailed placement in sub-10nm VLSI.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Finding placement-relevant clusters with fast modularity-based clustering.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Learning-based prediction of package power delivery network quality.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Silicon Photonics for Computing Systems.
ACM J. Emerg. Technol. Comput. Syst., 2018

Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Influence of Professor T. C. Hu's Works on Fundamental Approaches in Layout.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Machine Learning Applications in Physical Design: Recent Results and Directions.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Theory and Algorithms of Physical Design.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

TritonRoute: an initial detailed router for advanced VLSI technologies.
Proceedings of the International Conference on Computer-Aided Design, 2018

A cross-layer methodology for design and optimization of networks in 2.5D systems.
Proceedings of the International Conference on Computer-Aided Design, 2018

Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Reducing time and effort in IC implementation: a roadmap of challenges and solutions.
Proceedings of the 55th Annual Design Automation Conference, 2018

A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions.
Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018

New directions for learning-based IC design tools and methodologies.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Practical Approximations of Steiner Trees in Uniform Orientation Metrics.
Proceedings of the Handbook of Approximation Algorithms and Metaheuristics, 2018

2017
Guest Editorial: Alternative Computing and Machine Learning for Internet of Things.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Logic Design Partitioning for Stacked Power Domains.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Optimal Scheduling and Allocation for IC Design Management and Cost Reduction.
ACM Trans. Design Autom. Electr. Syst., 2017

MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Benchmarking of Mask Fracturing Heuristics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories.
ACM Trans. Archit. Code Optim., 2017

Trading Accuracy for Energy in Stochastic Circuit Design.
ACM J. Emerg. Technol. Comput. Syst., 2017

Revisiting 3DIC benefit with multiple tiers.
Integr., 2017

Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.
Proceedings of the 54th Annual Design Automation Conference, 2017

Floorplan and placement methodology for improved energy reduction in stacked power-domain design.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
BEOL stack-aware routability prediction from placement using data mining techniques.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Improved flop tray-based design implementation for power reduction.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Measuring progress and value of IC implementation technology.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Comprehensive optimization of scan chain timing during late-stage IC implementation.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Learning-based prediction of embedded memory timing failures during initial floorplan design.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Optimization of Overdrive Signoff in High-Performance and Low-Power ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Improved Methodology for Resilient Design Implementation.
ACM Trans. Design Autom. Electr. Syst., 2015

Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design.
ACM J. Emerg. Technol. Comput. Syst., 2015

ORION3.0: A Comprehensive NoC Router Estimation Tool.
IEEE Embed. Syst. Lett., 2015

SI for free: machine learning of interconnect coupling delay and transition effects.
Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

Multi-product floorplan and uncore design framework for chip multiprocessors.
Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

Clock clustering and IO optimization for 3D integration.
Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

Modeling the future of semiconductors (and test!).
Proceedings of the 2015 IEEE International Test Conference, 2015

Crosstalk-aware signal probability-based dynamic statistical timing analysis.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Toward Metrics of Design Automation Research Impact.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Evolving EDA Beyond its E-Roots: An Overview.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

New game, new goal posts: a recent history of timing closure.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router.
Proceedings of the 52nd Annual Design Automation Conference, 2015

3DIC benefit estimation and implementation guidance from 2DIC implementation.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors.
IEEE Trans. Very Large Scale Integr. Syst., 2014

On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Methodology for electromigration signoff in the presence of adaptive voltage scaling.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

Toward Holistic Modeling, Margining and Tolerance of IC Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Timing margin recovery with flexible flip-flop timing model.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Optimal reliability-constrained overdrive frequency selection in multicore systems.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Improved signoff methodology with tightened BEOL corners.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Benchmarking of mask fracturing heuristics.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Horizontal benchmark extension for improved assessment of physical CAD research.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Minimum implant area-aware gate sizing and placement.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A new methodology for reduced cost of resilience.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

OCV-aware top-level clock tree optimization.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Co-optimization of memory BIST grouping, test scheduling, and logic placement.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Mission profile aware IC design - A case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A deep learning methodology to proliferate golden signoff timing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Enhancing the Efficiency of Energy-Constrained DVFS Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Many-Core Token-Based Adaptive Power Gating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

High-dimensional metamodeling for prediction of clock tree synthesis outcomes.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Learning-based approximation of interconnect delay and slew in signoff timing tools.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Toward quantifying the IC design value of interconnect technology improvements.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Reliability-constrained die stacking order in 3DICs under manufacturing variability.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Statistical analysis and modeling for error composition in approximate computation circuits.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Incremental multiple-scan chain ordering for ECO flip-flop insertion.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

High-performance gate sizing with a signoff timer.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Enhanced metamodeling techniques for high-dimensional IC design estimation problems.
Proceedings of the Design, Automation and Test in Europe, 2013

Active-mode leakage reduction with data-retained power gating.
Proceedings of the Design, Automation and Test in Europe, 2013

Impact of adaptive voltage scaling on aging-aware signoff.
Proceedings of the Design, Automation and Test in Europe, 2013

Smart non-default routing for clock power reduction.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

The ITRS design technology and system drivers roadmap: process and status.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

On potential design impacts of electromigration awareness.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Optimization of overdrive signoff.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
ORION 2.0: A Power-Area Simulator for Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Predicting the future of information technology and society [The Road Ahead].
IEEE Des. Test Comput., 2012

Improved path clustering for adaptive path-delay testing.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Construction of realistic gate sizing benchmarks with known optimal solutions.
Proceedings of the International Symposium on Physical Design, 2012

Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph.
Proceedings of the International Symposium on Physical Design, 2012

TAP: token-based adaptive power gating.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Sensitivity-guided metaheuristics for accurate discrete gate sizing.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Tunable sensors for process-aware voltage scaling.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

MAPG: Memory access power gating.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Explicit modeling of control and data for improved NoC router estimation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Accuracy-configurable adder for approximate arithmetic designs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Big Chips.
IEEE Micro, 2011

Product Futures.
IEEE Des. Test Comput., 2011

Roadmapping Power.
IEEE Des. Test Comput., 2011

The Future of Signoff.
IEEE Des. Test Comput., 2011

Roads not taken.
IEEE Des. Test Comput., 2011

Design for manufacturability: Then and now.
IEEE Des. Test Comput., 2011

Mobile system considerations for SDRAM interface trends.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

Toward PDN resource estimation: A law of general power density.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

Stability and scalability in global routing.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

More realistic power grid verification based on hierarchical current and power constraints.
Proceedings of the 2011 International Symposium on Physical Design, 2011

VLSI Physical Design - From Graph Partitioning to Timing Closure.
Springer, ISBN: 978-90-481-9590-9, 2011

2010
Accurate Predictive Interconnect Modeling for System-Level Design.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Layout Decomposition Approaches for Double Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Accurate Machine-Learning-Based On-Chip Router Modeling.
IEEE Embed. Syst. Lett., 2010

When is 3D 2B?
IEEE Des. Test Comput., 2010

Scaling: More than Moore's law.
IEEE Des. Test Comput., 2010

Worst-case performance prediction under supply voltage and temperature variation.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Assessing chip-level impact of double patterning lithography.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Toward effective utilization of timing exceptions in design optimization.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Methodology from chaos in IC implementation.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Designing a processor from the ground up to allow voltage/reliability tradeoffs.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Trace-driven optimization of networks-on-chip configurations.
Proceedings of the 47th Design Automation Conference, 2010

Recovery-driven design: a power minimization methodology for error-tolerant processor modules.
Proceedings of the 47th Design Automation Conference, 2010

Eyecharts: constructive benchmarking of gate sizing heuristics.
Proceedings of the 47th Design Automation Conference, 2010

Improved on-chip router analytical power and area modeling.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Slack redistribution for graceful degradation under voltage overscaling.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Lens aberration aware placement for timing yield.
ACM Trans. Design Autom. Electr. Syst., 2009

Is overlay error more important than interconnect variations in double patterning?
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Revisiting the linear programming framework for leakage power vs. performance optimization.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration.
Proceedings of the Design, Automation and Test in Europe, 2009

Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
CMP Fill Synthesis.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

CMP Fill Synthesis: A Survey of Recent Studies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fast Dual-Graph-Based Hotspot Filtering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Defocus-Aware Leakage Estimation and Control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Quantified Impacts of Guardband Reduction on Design Process Outcomes.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

How to get real mad.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Layout decomposition for double patterning lithography.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

DFM in practice: hit or hype?
Proceedings of the 45th Design Automation Conference, 2008

Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.
Proceedings of the 45th Design Automation Conference, 2008

Bounded-lifetime integrated circuits.
Proceedings of the 45th Design Automation Conference, 2008

Investigation of diffusion rounding for post-lithography analysis.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Interconnect modeling for improved system-level design optimization.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Practical Approximations of Steiner Trees in Uniform Orientation Metrics.
Proceedings of the Handbook of Approximation Algorithms and Metaheuristics., 2007

Multicommodity Flow Algorithms for Buffered Global Routing.
Proceedings of the Handbook of Approximation Algorithms and Metaheuristics., 2007

Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Enhanced Design Flow and Optimizations for Multiproject Wafers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Statistical Timing Analysis in the Presence of Signal-Integrity Effects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L<sub>eff</sub> Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Detailed Placement for Enhanced Control of Resist and Etch CDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs.
IEEE Des. Test Comput., 2007

A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

On-Line Adjustable Buffering for Runtime Power Reduction.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Detailed placement for leakage reduction using systematic through-pitch variation.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Analytical thermal placement for VLSI lifetime improvement and minimum performance variation.
Proceedings of the 25th International Conference on Computer Design, 2007

Exploiting STI stress for performance.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Key directions and a roadmap for electrical design for manufacturability.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Design challenges at 65nm and beyond.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Line-End Shortening is Not Always a Failure.
Proceedings of the 44th Design Automation Conference, 2007

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

APlace: A High Quality, Large-Scale Analytical Placer.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006
A Fast Hierarchical Quadratic Placement Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Wirelength minimization for min-cut placements via placement feedback.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

New and improved BIST diagnosis methods from combinatorial Group testing theory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Computer-Aided Optimization of DNA Array Design and Manufacturing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Gate-length biasing for runtime-leakage control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Wafer Topography-Aware Optical Proximity Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Efficient Design and Analysis of Robust Power Distribution Meshes.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Generation of design guarantees for interconnect matching.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

A tale of two nets: studies of wirelength progression in physical design.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Statistical crosstalk aggressor alignment aware interconnect delay calculation.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Study of Floating Fill Impact on Interconnect Capacitance.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Impact of Gate-Length Biasing on Threshold-Voltage Selection.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Constructing Current-Based Gate Models Based on Existing Timing Library.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A faster implementation of APlace.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Efficient decoupling capacitor planning via convex programming methods.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Fill for shallow trench isolation CMP.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Statistical gate delay calculation with crosstalk alignment consideration.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Lens aberration aware timing-driven placement.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Standard cell library optimization for leakage reduction.
Proceedings of the 43rd Design Automation Conference, 2006

DFM: where's the proof of value?
Proceedings of the 43rd Design Automation Conference, 2006

CAD challenges for leading-edge multimedia designs.
Proceedings of the 43rd Design Automation Conference, 2006

Timing-driven Steiner trees are (practically) free.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Routing-aware scan chain ordering.
ACM Trans. Design Autom. Electr. Syst., 2005

Implementation and extensibility of an analytic placer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Layout-aware scan chain synthesis for improved path delay fault coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Compressible area fill synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

The Y architecture for on-chip interconnect: analysis and methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

DAC Highlights.
IEEE Des. Test Comput., 2005

Multicommodity Flow Algorithms for Buffered Global Routing
CoRR, 2005

Performance Driven OPC for Mask Cost Reduction.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

APlace: a general analytic placement framework.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Evaluation of placer suboptimality via zero-change netlist transformations.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.
Proceedings of the 2005 International Symposium on Physical Design, 2005

A semi-persistent clustering technique for VLSI circuit placement.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Defocus-aware leakage estimation and control.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Supply Voltage Degradation Aware Analytical Placement.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Architecture and details of a high quality, large-scale analytical placer.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Intrinsic shortest path length: a new, accurate a priori wirelength estimator.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Fast and efficient phase conflict detection and correction in standard-cell layouts.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Bright-Field AAPSM Conflict Detection and Correction.
Proceedings of the 2005 Design, 2005

Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions.
Proceedings of the 42nd Design Automation Conference, 2005

Power-aware placement.
Proceedings of the 42nd Design Automation Conference, 2005

Detailed placement for improved depth of focus and CD control.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Nontree routing for reliability and yield improvement [IC layout].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Effective iterative techniques for fingerprinting design IP.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Match twice and stitch: a new TSP tour construction heuristic.
Oper. Res. Lett., 2004

Scalable Heuristics for Design of DNA Probe Arrays.
J. Comput. Biol., 2004

Guest Editors' Introduction: RTL to GDSII - From Foilware to Standard Practice.
IEEE Des. Test Comput., 2004

2003 Technology Roadmap for Semiconductors.
Computer, 2004

Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Investigation of performance metrics for interconnect stack architectures.
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

Manufacturability .
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Multi-project reticle floorplanning and wafer dicing.
Proceedings of the 2004 International Symposium on Physical Design, 2004

Evaluation of the new OASIS format for layout fill compression.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

An analytic placer for mixed-size placement and timing-driven placement.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

On legalization of row-based placements.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Boosting: Min-Cut Placement with Improved Signal Delay.
Proceedings of the 2004 Design, 2004

Placement feedback: a concept and method for better min-cut placements.
Proceedings of the 41th Design Automation Conference, 2004

Selective gate-length biasing for cost-effective runtime leakage control.
Proceedings of the 41th Design Automation Conference, 2004

Toward a methodology for manufacturability-driven design rule exploration.
Proceedings of the 41th Design Automation Conference, 2004

Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions.
Proceedings of the 41th Design Automation Conference, 2004

Combinatorial group testing methods for the BIST diagnosis problem.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Optimal planning for mesh-based power distribution.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Improved a priori interconnect predictions and technology extrapolation in the GTX system.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Hierarchical whitespace allocation in top-down placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Minimum buffered routing with bounded capacitive load for slew rate and reliability control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

On the skew-bounded minimum-buffer routing tree problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

How much variability can designers tolerate?
IEEE Des. Test Comput., 2003

Bringing down NRE.
IEEE Des. Test Comput., 2003

Error Tolerance.
IEEE Des. Test Comput., 2003

Accurate pseudo-constructive wirelength and congestion estimation.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Engineering a scalable placement heuristic for DNA probe arrays.
Proceedings of the Sventh Annual International Conference on Computational Biology, 2003

Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

A Proposal for Routing-Based Timing-Driven Scan Chain Ordering.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Quantifying Error in Dynamic Power Estimation of CMOS Circuits.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Research directions for coevolution of rules and routers.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Design Flow Enhancements for DNA Arrays.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Evaluation of Placement Techniques for DNA Probe Array Layout.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Manufacturing-Aware Physical Design.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A Novel Metric for Interconnect Architecture Performance.
Proceedings of the 2003 Design, 2003

Area Fill Generation With Inherent Data Volume Reduction.
Proceedings of the 2003 Design, 2003

Nanometer design: place your bets.
Proceedings of the 40th Design Automation Conference, 2003

A cost-driven lithographic correction methodology based on off-the-shelf sizing tools.
Proceedings of the 40th Design Automation Conference, 2003

Performance-impact limited area fill synthesis.
Proceedings of the 40th Design Automation Conference, 2003

An algebraic multigrid solver for analytical placement with layout based clustering.
Proceedings of the 40th Design Automation Conference, 2003

Highly scalable algorithms for rectilinear and octilinear Steiner trees.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Toward better wireload models in the presence of obstacles.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Provably good global buffering by generalized multiterminalmulticommodity flow approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Area fill synthesis for uniform layout density.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Asymmetric Binary Covering Codes.
J. Comb. Theory, Ser. A, 2002

The Road Ahead: The significance of packaging.
IEEE Des. Test Comput., 2002

Variability.
IEEE Des. Test Comput., 2002

2001 Technology Roadmap for Semiconductors.
Computer, 2002

Border Length Minimization in DNA Array Design.
Proceedings of the Algorithms in Bioinformatics, Second International Workshop, 2002

Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

A New Design Cost Model for the 2001 ITRS (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Measurement of Inherent Noise in EDA Tools.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Min-max placement for large-scale timing optimization.
Proceedings of 2002 International Symposium on Physical Design, 2002

A roadmap and vision for physical design.
Proceedings of 2002 International Symposium on Physical Design, 2002

Closing the smoothness and uniformity gap in area fill synthesis.
Proceedings of 2002 International Symposium on Physical Design, 2002

Auctions with Buyer Preferences.
Proceedings of the Information Systems: The e-Business Challenge, 2002

Non-tree routing for reliability and yield improvement.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Tools or users: which is the bigger bottleneck?
Proceedings of the 39th Design Automation Conference, 2002

2001
Toward accurate models of achievable routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Constraint-based watermarking techniques for design IP protection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Limitations and challenges of computer-aided design technology for CMOS VLSI.
Proc. IEEE, 2001

Guest Editor's Introduction: Roadmaps and Visions for Design and Test.
IEEE Des. Test Comput., 2001

Practical Approximation Algorithms for Separable Packing Linear Programs.
Proceedings of the Algorithms and Data Structures, 7th International Workshop, 2001

Interconnect implications of growth-based structural models for VLSI circuits.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

On the relevance of wire load models.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Noise Model for Multiple Segmented Coupled RC Interconnects.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

A System for Automatic Recording and Prediction of Design Quality Metrics.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Design Metrics to Achieve Design Quality.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Buffered Steiner trees for difficult instances.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Panel: Is Nanometer Design Under Control?
Proceedings of the 38th Design Automation Conference, 2001

Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.
Proceedings of ASP-DAC 2001, 2001

New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout.
Proceedings of ASP-DAC 2001, 2001

Design technology productivity in the DSM era (invited talk).
Proceedings of ASP-DAC 2001, 2001

Provably good global buffering by multi-terminal multicommodity flow approximation.
Proceedings of ASP-DAC 2001, 2001

Hierarchical dummy fill for process uniformity.
Proceedings of ASP-DAC 2001, 2001

2000
Iterative Partitioning with Varying Node Weights.
VLSI Design, 2000

Optimal partitioners and end-case placers for standard-cell layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Optimal phase conflict removal for layout of dark field alternatingphase shifting masks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Hypergraph partitioning with fixed vertices [VLSI CAD].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning.
ACM J. Exp. Algorithmics, 2000

Wiring layer assignments with consistent stage delays.
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Admissibility Proofs for the LCS* Algorithm.
Proceedings of the Advances in Artificial Intelligence, 2000

Requirements for models of achievable routing.
Proceedings of the 2000 International Symposium on Physical Design, 2000

Classical floorplanning harmful?
Proceedings of the 2000 International Symposium on Physical Design, 2000

On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Provably Good Global Buffering Using an Available Buffer Block Plan.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

EDA meets.COM (panel session): how E-services will change the EDA business model.
Proceedings of the 37th Conference on Design Automation, 2000

On switch factor based analysis of coupled <i>RC</i> interconnects.
Proceedings of the 37th Conference on Design Automation, 2000

METRICS: a system architecture for design process optimization.
Proceedings of the 37th Conference on Design Automation, 2000

Practical iterated fill synthesis for CMP uniformity.
Proceedings of the 37th Conference on Design Automation, 2000

Can recursive bisection alone produce routable placements?
Proceedings of the 37th Conference on Design Automation, 2000

GTX: the MARCO GSRC technology extrapolation system.
Proceedings of the 37th Conference on Design Automation, 2000

Monte-Carlo algorithms for layout density control.
Proceedings of ASP-DAC 2000, 2000

Improved algorithms for hypergraph bipartitioning.
Proceedings of ASP-DAC 2000, 2000

1999
Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs.
VLSI Design, 1999

Analytical Engines are Unnecessary in Top-down Partitioning-based Placement.
VLSI Design, 1999

Filling algorithms and analyses for layout density control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

On wirelength estimations for row-based placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Spectral Partitioning with Multiple Eigenvectors.
Discret. Appl. Math., 1999

The T-join Problem in Sparse Graphs: Applications to Phase Assignment Problem in VLSI Mask Layout.
Proceedings of the Algorithms and Data Structures, 6th International Workshop, 1999

New and Exact Filling Algorithms for Layout Density Control.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Interconnect Optimization Strategies for High-Performance VLSI Designs.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Improved Effective Capacitance Computations for Use in Logic and Layout Optimization.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Subwavelength optical lithography: challenges and impact on physical design.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Optimal phase conflict removal for layout of dark field alternating phase shifting masks.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Partitioning with terminals: a "new" problem and new benchmarks.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Copy detection for intellectual property protection of VLSI designs.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

The associative-skew clock routing problem.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Subwavelength Lithography: How Will It Affect Your Design Flow? (Panel).
Proceedings of the 36th Conference on Design Automation, 1999

Subwavelength Lithography and Its Potential Impact on Design and EDA.
Proceedings of the 36th Conference on Design Automation, 1999

Hypergraph Partitioning with Fixed Vertices.
Proceedings of the 36th Conference on Design Automation, 1999

Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting.
Proceedings of the 36th Conference on Design Automation, 1999

Optimization of Linear Placements for Wirelength Minimization with Free Sites.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

New Multilevel and Hierarchical Algorithms for Layout Density Control.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Function Smoothing with Applications to VLSI Layout.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning.
Proceedings of the Algorithm Engineering and Experimentation, 1999

1998
Bounded-skew clock and Steiner routing.
ACM Trans. Design Autom. Electr. Syst., 1998

Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Multilevel circuit partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Faster minimization of linear wirelength for global placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

How to test a tree.
Networks, 1998

Filling and slotting: analysis and algorithms.
Proceedings of the 1998 International Symposium on Physical Design, 1998

New efficient algorithms for computing effective capacitance.
Proceedings of the 1998 International Symposium on Physical Design, 1998

Futures for partitioning in physical design (tutorial).
Proceedings of the 1998 International Symposium on Physical Design, 1998

Interconnect Tuning Strategies for High-Performance Ics.
Proceedings of the 1998 Design, 1998

Robust IP Watermarking Methodologies for Physical Design.
Proceedings of the 35th Conference on Design Automation, 1998

Watermarking Techniques for Intellectual Property Protection.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Practical Bounded-Skew Clock Routing.
J. VLSI Signal Process., 1997

Analysis of RC interconnections under ramp input.
ACM Trans. Design Autom. Electr. Syst., 1997

An analytical delay model for RLC interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

On implementation choices for iterative improvement partitioning algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Improved Large-Step Markov Chain Variants for the Symmetric TSP.
J. Heuristics, 1997

Cooperative Mobile Robotics: Antecedents and Directions.
Auton. Robots, 1997

Partitioning-based standard-cell global placement with an exact objective.
Proceedings of the 1997 International Symposium on Physical Design, 1997

Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design.
Proceedings of the 1997 International Symposium on Physical Design, 1997

Faster minimization of linear wirelength for global placement.
Proceedings of the 1997 International Symposium on Physical Design, 1997

More Practical Bounded-Skew Clock Routing.
Proceedings of the 34st Conference on Design Automation, 1997

Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology.
Proceedings of the 34st Conference on Design Automation, 1997

1996
A general framework for vertex orderings with applications to circuit clustering.
IEEE Trans. Very Large Scale Integr. Syst., 1996

Planar-DME: a single-layer zero-skew clock tree router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Analytical delay models for VLSI interconnects under ramp input.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Near-optimal critical sink routing tree constructions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Multiway partitioning via geometric embeddings, orderings, and dynamic programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Prim-Dijkstra tradeoffs for improved performance-driven routing tree design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Recent directions in netlist partitioning: a survey.
Integr., 1995

Old Bachelor Acceptance: A New Class of Non-Monotone Threshold Accepting Methods.
INFORMS J. Comput., 1995

Cooperative mobile robotics: antecedents and directions.
Proceedings of IEEE/RSJ International Conference on Intelligent Robots and Systems, 1995

Toward More Powerful Recombinations.
Proceedings of the 6th International Conference on Genetic Algorithms, 1995

Bounded-skew clock and Steiner routing under Elmore delay.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

When clusters meet partitions: new density-based methods for circuit decomposition.
Proceedings of the 1995 European Design and Test Conference, 1995

On the Bounded-Skew Clock and Steiner Routing Problems.
Proceedings of the 32st Conference on Design Automation, 1995

Quantified Suboptimality of VLSI Layout Heuristics.
Proceedings of the 32st Conference on Design Automation, 1995

1994
On the Minimum Density Interconnection Tree Problem.
VLSI Design, 1994

On the intrinsic Rent parameter and spectra-based partitioning methodologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

A new adaptive multi-start technique for combinatorial global optimizations.
Oper. Res. Lett., 1994

Low-cost single-layer clock trees with exact zero Elmore delay skew.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A general framework for vertex orderings, with applications to netlist clustering.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay.
Proceedings of the Proceedings EURO-DAC'94, 1994

Optimal equivalent circuits for interconnect delay calculations using moments.
Proceedings of the Proceedings EURO-DAC'94, 1994

Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model.
Proceedings of the 31st Conference on Design Automation, 1994

Rectilinear Steiner Trees with Minimum Elmore Delay.
Proceedings of the 31st Conference on Design Automation, 1994

Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Optimal robust path planning in general environments.
IEEE Trans. Robotics Autom., 1993

Matching-based methods for high-performance clock routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Simulated annealing of neural networks: The 'cooling' strategy reconsidered.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Minimum Density Interconneciton Trees.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Fidelity and Near-Optimality of Elmore-Based Routing Constructions.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD.
Proceedings of the European Design Automation Conference 1993, 1993

High-Performance Routing Trees With Identified Critical Sinks.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

A new class of iterative Steiner tree heuristics with good performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

New spectral methods for ratio cut partitioning and clustering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Provably good performance-driven global routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.
IEEE Des. Test Comput., 1992

An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

A new approach to effective circuit clustering.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Net Partitions Yield Better Module Partitions.
Proceedings of the 29th Design Automation Conference, 1992

1991
Optimal algorithms for extracting spatial regularity in images.
Pattern Recognit. Lett., 1991

An Effective Analog Approach to Steiner Routing.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Performance-Driven Global Routing for Cell Based ICs.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Fast Spectral Methods for Ratio Cut Partitioning and Clustering.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

High-Performance Clock Routing Based on Recursive Geometric Aatching.
Proceedings of the 28th Design Automation Conference, 1991

1990
A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-Approach.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Every Tree is Graceful (But Some are More Graceful than Others).
Proceedings of the Applied Geometry And Discrete Mathematics, 1990

1989
Fast Hypergraph Partition.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989


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