Yi Cai

Orcid: 0000-0001-8264-3357

Affiliations:
  • Tsinghua University, Beijing National Research Center for Information Science and Technology, BNRist, Beijing, China
  • Tsinghua University, Department of Electronic Engineering, Beijing, China


According to our database1, Yi Cai authored at least 20 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Memory-Oriented Structural Pruning for Efficient Image Restoration.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

Ensemble-in-One: Ensemble Learning within Random Gated Networks for Enhanced Adversarial Robustness.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022
WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

CLOSE: Curriculum Learning on the Sharing Extent Towards Better One-Shot NAS.
Proceedings of the Computer Vision - ECCV 2022, 2022

2021
Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing With Ferroelectric FETs.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Ensemble-in-One: Learning Ensemble within Random Gated Networks for Enhanced Adversarial Robustness.
CoRR, 2021

3M-AI: A Multi-task and Multi-core Virtualization Framework for Multi-FPGA AI Systems in the Cloud.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Reliability-Aware Training and Performance Modeling for Processing-In-Memory Systems.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

MNSIM-TIME: Performance Modeling Framework for Training-In-Memory Architectures.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Low Bit-Width Convolutional Neural Network on RRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Long Live TIME: Improving Lifetime and Security for NVM-Based Training-in-Memory Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Enabling Secure NVM-Based in-Memory Neural Network Computing by Sparse Fast Gradient Encryption.
IEEE Trans. Computers, 2020

Security Enhancement for RRAM Computing System through Obfuscating Crossbar Row Connections.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient Encryption.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
Rescuing memristor-based computing with non-linear resistance levels.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification.
Proceedings of the 55th Annual Design Automation Conference, 2018

Training low bitwidth convolutional neural network on RRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017


  Loading...