Yongpan Liu
Orcid: 0000-0002-4892-2309
According to our database1,
Yongpan Liu
authored at least 233 papers
between 2005 and 2024.
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Bibliography
2024
Weight and Multiply-Accumulation Sparsity-Aware Non-Volatile Computing-in-Memory System.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
ACM Trans. Design Autom. Electr. Syst., March, 2024
ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024
TFT-Based Near-Sensor In-Memory Computing: Circuits and Architecture Perspectives of Large-Area eDRAM and ROM CiM Chips.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility.
IEEE Trans. Emerg. Top. Comput., 2024
34.7 A 28nm 2.4Mb/mm<sup>2</sup> 6.9 - 16.3TOPS/mm<sup>2</sup> eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Modularized Equalization Architecture With Transformer-Based Integrating Voltage Equalizer for the Series-Connected Battery Pack in Electric Bicycles.
IEEE Trans. Ind. Electron., July, 2023
SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
IEEE J. Solid State Circuits, May, 2023
FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
Reliable and Efficient Parallel Checkpointing Framework for Nonvolatile Processor With Concurrent Peripherals.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for Large-Scaled Voxel-Based Point Cloud Network.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators.
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023
Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
SOLE: Hardware-Software Co-design of Softmax and LayerNorm for Efficient Transformer Inference.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
A 28nm 1.07TFLOPS/mm<sup>2</sup> Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Semantic Guided Fine-Grained Point Cloud Quantization Framework for 3D Object Detection.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
A Demonstration Platform for Large-Scaled Point Cloud Network Based on 28nm 2D/3D Unified Sparse Convolution Accelerator.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
2022
CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Neural Networks Learn. Syst., 2022
Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.
IEEE J. Solid State Circuits, 2022
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications.
IEEE J. Solid State Circuits, 2022
Guest Editorial: ACM JETC Special Issue on Hardware-Aware Learning for Medical Applications.
ACM J. Emerg. Technol. Comput. Syst., 2022
A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface.
CoRR, 2022
Ferroelectric FET-based strong physical unclonable function: a low-power, high-reliable and reconfigurable solution for Internet-of-Things security.
CoRR, 2022
GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph.
CoRR, 2022
ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key.
CoRR, 2022
FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications.
CoRR, 2022
Mixed-Precision Continual Learning Based on Computational Resistance Random Access Memory.
Adv. Intell. Syst., 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Dynamic CNN Accelerator Supporting Efficient Filter Generator with Kernel Enhancement and Online Channel Pruning.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays.
IEEE Trans. Very Large Scale Integr. Syst., 2021
MaxTracker: Continuously Tracking the Maximum Computation Progress for Energy Harvesting ReRAM-based CNN Accelerators.
ACM Trans. Embed. Comput. Syst., 2021
Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing With Ferroelectric FETs.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration.
IEEE J. Solid State Circuits, 2021
High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021
A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Session 15 Overview: Compute-in-Memory Processors for Deep Neural Networks Machine Learning Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Exploiting FeFET Switching Stochasticity for Low-Power Reconfigurable Physical Unclonable Function.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional Tracking.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object Detection.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
IEEE Trans. Circuits Syst., 2020
A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
GAAS: An Efficient Group Associated Architecture and Scheduler Module for Sparse CNN Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Sensors, 2020
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
Low Overhead Online Data Flow Tracking for Intermittently Powered Non-Volatile FPGAs.
ACM J. Emerg. Technol. Comput. Syst., 2020
CoRR, 2020
High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning.
CoRR, 2020
ADMP: An Adversarial Double Masks Based Pruning Framework For Unsupervised Cross-Domain Compression.
CoRR, 2020
14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Multi-channel precision-sparsity-adapted inter-frame differential data codec for video neural network processor.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
High-Quality Single-Model Deep Video Compression with Frame-Conv3D and Multi-frame Differential Modulation.
Proceedings of the Computer Vision - ECCV 2020, 2020
High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
A 112-765 GOPS/W FPGA-based CNN Accelerator using Importance Map Guided Adaptive Activation Sparsification for Pix2pix Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
A Task Failure Rate Aware Dual-Channel Solar Power System for Nonvolatile Sensor Nodes.
ACM Trans. Embed. Comput. Syst., 2019
A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
An Auto Loss Co Jian Zhaompensation System for Capacitive-Coupled Body Channel Communication.
IEEE Trans. Biomed. Circuits Syst., 2019
Dynamic Channel Modeling and OFDM System Analysis for Capacitive Coupling Body Channel Communication.
IEEE Trans. Biomed. Circuits Syst., 2019
A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices.
IEEE Micro, 2019
A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.
IEEE J. Solid State Circuits, 2019
A global and updatable ECG beat classification system based on recurrent neural networks and active learning.
Inf. Sci., 2019
IEEE Des. Test, 2019
A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond.
CoRR, 2019
Progressive DNN Compression: A Key to Achieve Ultra-High Weight Pruning and Quantization Rates using ADMM.
CoRR, 2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm<sup>2</sup>and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
A 4-Mbps 41-pJ/bit On-off Keying Transceiver for Body-channel Communication with Enhanced Auto Loss Compensation Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2018
ACM Trans. Design Autom. Electr. Syst., 2018
Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors.
IEEE Micro, 2018
Efficient energy management by exploiting retention state for self-powered nonvolatile processors.
J. Syst. Archit., 2018
Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
An extensible system simulator for intermittently-powered multiple-peripheral IoT devices.
Proceedings of the 6th International Workshop on Energy Harvesting & Energy-Neutral Sensing Systems, 2018
Prototyping Energy Harvesting Powered Systems with Nonvolatile Processor (Invited Paper).
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018
A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware Support.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Live Demonstration: A self-powered ultraviolet radiation monitoring platform based on nonvolatile processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
An Investigation on Inter-degeneration Effect in Body Channel Based Multi-node Wireless Power Transfer.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems.
ACM Trans. Embed. Comput. Syst., 2017
Maximum Energy Efficiency Tracking Circuits for Converter-Less Energy Harvesting Sensor Nodes.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A Ferroelectric Nonvolatile Processor with 46 $\mu $ s System-Level Wake-up Time and 14 $\mu $ s Sleep Time for Energy Harvesting Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.
IEEE J. Solid State Circuits, 2017
A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.
IEEE J. Solid State Circuits, 2017
IEEE Des. Test, 2017
Retention state-enabled and progress-driven energy management for self-powered nonvolatile processors.
Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
A lightweight progress maximization scheduler for non-volatile processor under unstable energy harvesting.
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017
Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
An 8b 0.8kS/s configurable VCO-based ADC using oxide TFTs with Inkjet printing interconnection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.
Proceedings of the 54th Annual Design Automation Conference, 2017
Retention state-aware energy management for efficient nonvolatile processors: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications.
ACM Trans. Design Autom. Electr. Syst., 2016
Wear-Leveling Aware Page Management for Non-Volatile Main Memory on Embedded Systems.
IEEE Trans. Multi Scale Comput. Syst., 2016
A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power.
IEEE Micro, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Dynamic converter reconfiguration for near-threshold non-volatile processors using in-door energy harvesting.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
HW/SW co-design of nonvolatile IO system in energy harvesting sensor nodes for optimal data acquisition.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Proceedings of the 13th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2016
CP-FPGA: Computation data-aware software/hardware co-design for nonvolatile FPGAs based on checkpointing techniques.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Micro, 2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Proceedings of the 2015 IEEE Real-Time Systems Symposium, 2015
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Multi-source energy harvesting management and optimization for non-volatile processors.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015
Software assisted non-volatile register reduction for energy harvesting based cyber-physical system.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 2015 International Conference on Compilers, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A high-efficiency dual-channel photovoltaic power system for nonvolatile sensor nodes.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Storage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessor.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors.
Proceedings of the Design, Automation and Test in Europe, 2013
Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications.
Proceedings of the Design, Automation and Test in Europe, 2013
Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Lifetime-Aware Battery Allocation for Wireless Sensor Network under Cost Constraints.
IEICE Trans. Commun., 2012
A low-complexity symbol-level differential detection scheme for IEEE 802.15.4 O-QPSK signals.
Proceedings of the International Conference on Wireless Communications and Signal Processing, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
An energy harvesting nonvolatile sensor node and its application to distributed moving object detection.
Proceedings of the 11th International Conference on Information Processing in Sensor Networks (co-located with CPS Week 2012), 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression.
IEICE Trans. Electron., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Sensors, 2010
IEICE Trans. Electron., 2010
IEICE Trans. Commun., 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2009
Battery allocation for wireless sensor network lifetime maximization under cost constraints.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Energy efficient architecture of sensor network node based on compression accelerator.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks.
Proceedings of the Design, Automation and Test in Europe, 2009
2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
A Hybrid Genetic Algorithm with Critical Primary Inputs Sharing and Minor Primary Inputs Bits Climbing for Circuit Maximum Power Estimation.
Proceedings of the Third International Conference on Natural Computation, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization.
Proceedings of the Advances in Natural Computation, Second International Conference, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Proceedings of the Advances in Natural Computation, First International Conference, 2005