Huazhong Yang

According to our database1, Huazhong Yang authored at least 349 papers between 1999 and 2019.

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Bibliography

2019
[DL] A Survey of FPGA-based Neural Network Inference Accelerators.
TRETS, 2019

A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization.
IEEE Trans. on Circuits and Systems, 2019

A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation.
IEEE Trans. on Circuits and Systems, 2019

Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs.
IEEE Trans. on Circuits and Systems, 2019

GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.
J. Solid-State Circuits, 2019

A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40°C to 85°C.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

A Fine-Grained Sparse Accelerator for Multi-Precision DNN.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Compressed CNN Training with FPGA-based Accelerator.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors.
IEEE Trans. VLSI Syst., 2018

Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA.
TRETS, 2018

Bidirectional Database Storage and SQL Query Exploiting RRAM-Based Process-in-Memory Structure.
TOS, 2018

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Five-Tissue-Layer Human Body Communication Circuit Model Tunable to Individual Characteristics.
IEEE Trans. Biomed. Circuits and Systems, 2018

All-in-focus with directional-max-gradient flow and labeled iterative depth propagation.
Pattern Recognition, 2018

High linearity source-follower buffer based analog memory for analog convolutional neural network.
Microelectronics Journal, 2018

Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL.
Int. J. Reconfig. Comp., 2018

Redundancy-bandwidth scalable techniques for signal-independent element transition rates in high-speed current-steering DACs.
I. J. Circuit Theory and Applications, 2018

Stuck-at Fault Tolerance in RRAM Computing Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Nonparametric Topic Modeling with Neural Inference.
CoRR, 2018

Hu-Fu: Hardware and Software Collaborative Attack Framework against Neural Networks.
CoRR, 2018

Two-Stream Binocular Network: Accurate Near Field Finger Detection Based On Binocular Images.
CoRR, 2018

Interactive Hand Pose Estimation: Boosting accuracy in localizing extended finger joints.
CoRR, 2018

Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Interactive Hand Pose Estimation: Boosting accuracy in localizing extended finger joints.
Proceedings of the Visual Information Processing and Communication IX, Burlingame, CA, USA, 28 January 2018, 2018

Energy-Efficient SRAM Design with Data-Aware Dual-Modes L0T Storage Cell for CNN Processors.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

An extensible system simulator for intermittently-powered multiple-peripheral IoT devices.
Proceedings of the 6th International Workshop on Energy Harvesting & Energy-Neutral Sensing Systems, 2018

Energy-efficient MFCC extraction architecture in mixed-signal domain for automatic speech recognition.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Energy Efficient ApproxSIFT Implementation for Image Mosaic with Approximate Computing Technologies.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware Support.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Hu-Fu: Hardware and Software Collaborative Attack Framework Against Neural Networks.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

RRAM Based Buffer Design for Energy Efficient CNN Accelerator.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

An Auto Loss Compensation System for Non-contact Capacitive Coupled Body Channel Communication.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

MINTIN: Maxout-Based and Input-Normalized Transformation Invariant Neural Network.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

Scene-Adaptive Image Acquisition for Focus Stacking.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

An Efficient Reconfigurable Framework for General Purpose CNN-RNN Models on FPGAs.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Approximate On-chip Memory Optimization Method For Deep Residual Networks.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Mixed size crossbar based RRAM CNN accelerator with overlapped mapping method.
Proceedings of the International Conference on Computer-Aided Design, 2018

NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Bidirectional Recurrent Neural Network And Convolutional Neural Network (BiRCNN) For ECG Beat Classification.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Real-Time ECG Delineation with Randomly Selected Wavelet Transform Feature and Random Walk Estimation.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Channel Loss in Contactless Human Body Communication.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Region Aggregation Network: Improving Convolutional Neural Network for ECG Characteristic Detection.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Spatial-Temporal Attention Res-TCN for Skeleton-Based Dynamic Hand Gesture Recognition.
Proceedings of the Computer Vision - ECCV 2018 Workshops, 2018

Real-time object detection towards high power efficiency.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Rescuing memristor-based computing with non-linear resistance levels.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

HyVE: Hybrid vertex-edge memory hierarchy for energy-efficient graph processing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Calibrating process variation at system level with in-situ low-precision transfer learning for analog neural network processors.
Proceedings of the 55th Annual Design Automation Conference, 2018

Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification.
Proceedings of the 55th Annual Design Automation Conference, 2018

Bi-stream Region Ensemble Network: Promoting Accuracy in Fingertip Localization from Stereo Images.
Proceedings of the British Machine Vision Conference 2018, 2018

An Investigation on Inter-degeneration Effect in Body Channel Based Multi-node Wireless Power Transfer.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Training low bitwidth convolutional neural network on RRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

CMOS Image Sensor Data-Readout Method for Convolutional Operations with Processing Near Sensor Architecture.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing Optimization.
IEEE Trans. VLSI Syst., 2017

DVFS-Based Long-Term Task Scheduling for Dual-Channel Solar-Powered Sensor Nodes.
IEEE Trans. VLSI Syst., 2017

Maximum Energy Efficiency Tracking Circuits for Converter-Less Energy Harvesting Sensor Nodes.
IEEE Trans. on Circuits and Systems, 2017

A Ferroelectric Nonvolatile Processor with 46 $\mu $ s System-Level Wake-up Time and 14 $\mu $ s Sleep Time for Energy Harvesting Applications.
IEEE Trans. on Circuits and Systems, 2017

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

An Investigation on Ground Electrodes of Capacitive Coupling Human Body Communication.
IEEE Trans. Biomed. Circuits and Systems, 2017

A Self-Adaptive Capacitive Compensation Technique for Body Channel Communication.
IEEE Trans. Biomed. Circuits and Systems, 2017

All-Digital Galvanically-Coupled BCC Receiver Resilient to Frequency Misalignment.
IEEE Trans. Biomed. Circuits and Systems, 2017

Software-Hardware Codesign for Efficient Neural Network Acceleration.
IEEE Micro, 2017

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.
J. Solid-State Circuits, 2017

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.
J. Solid-State Circuits, 2017

Multistage Latency Adders Architecture Employing Approximate Computing.
Journal of Circuits, Systems, and Computers, 2017

A Survey of FPGA Based Neural Network Accelerator.
CoRR, 2017

A Deep Learning Approach for Blind Drift Calibration of Sensor Networks.
CoRR, 2017

Region Ensemble Network: Improving Convolutional Network for Hand Pose Estimation.
CoRR, 2017

Two-stream binocular network: Accurate near field finger detection based on binocular images.
Proceedings of the 2017 IEEE Visual Communications and Image Processing, 2017

Energy-efficient SQL query exploiting RRAM-based process-in-memory structure.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

AIsim: Functional Simulator for Analog-to-Information Perceptual Systems.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

AICNN: Implementing Typical CNN Algorithms with Analog-to-Information Conversion Architecture.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Low-overhead implementation of logic encryption using gate replacement techniques.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

An 8b 0.8kS/s configurable VCO-based ADC using oxide TFTs with Inkjet printing interconnection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

From "MISSION: IMPOSSIBLE" to mission possible: Fully flexible intelligent contact lens for image classification with analog-to-information processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Region ensemble network: Improving convolutional network for hand pose estimation.
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017

Depth-Based Focus Stacking with Labeled-Laplacian Propagation.
Proceedings of the Image and Graphics - 9th International Conference, 2017

CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Evaluating Data Resilience in CNNs from an Approximate Memory Perspective.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Streaming sorting network based BWT acceleration on FPGA for lossless compression.
Proceedings of the International Conference on Field Programmable Technology, 2017

Instruction driven cross-layer CNN accelerator with winograd transformation on FPGA.
Proceedings of the International Conference on Field Programmable Technology, 2017

ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.
Proceedings of the 54th Annual Design Automation Conference, 2017

TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

A miniaturized wearable wireless hand gesture recognition system employing deep-forest classifier.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Using human body as a monopole antenna for energy harvesting from ambient electromagnetic energy.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Live demonstration: A hand gesture recognition wristband employing low power body channel communication.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Binary convolutional neural network on RRAM.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Computation-oriented fault-tolerance schemes for RRAM computing systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications.
ACM Trans. Design Autom. Electr. Syst., 2016

A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution.
IEEE Trans. on Circuits and Systems, 2016

Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Host cancelation-based spread spectrum watermarking for audio anti-piracy over Internet.
Security and Communication Networks, 2016

Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication.
J. Comput. Sci. Technol., 2016

Spread spectrum audio watermarking based on perceptual characteristic aware extraction.
IET Signal Processing, 2016

A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing.
IEICE Electronic Express, 2016

Exploring the Precision Limitation for RRAM-Based Analog Approximate Computing.
IEEE Design & Test, 2016

A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors.
CoRR, 2016

ESE: Efficient Speech Recognition Engine with Compressed LSTM on FPGA.
CoRR, 2016

A compare-and-select error tolerant scheme for nonvolatile processors.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Approximate Adder with Hybrid Prediction and Error Compensation Technique.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

An ultra-fast and low-power design of analog circuit network for DoG pyramid construction of SIFT algorithm.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

SATS: An Ultra-Low Power Time Synchronization for Solar Energy Harvesting WSNs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Low power Convolutional Neural Networks on a chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A self-adaptive body channel communication scheme for backward path loss reduction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

NXgraph: An efficient graph processing system on a single machine.
Proceedings of the 32nd IEEE International Conference on Data Engineering, 2016

A precision-improved processing architecture of physical computing for energy-efficient SIFT feature extraction.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

From model to FPGA: Software-hardware co-design for efficient neural network acceleration.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

Approximate Frequent Itemset Mining for streaming data on FPGA.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGA.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

MNSIM: Simulation platform for memristor-based neuromorphic computing system.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Sparsity-oriented sparse solver design for circuit simulation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Switched by input: power efficient structure for RRAM-based convolutional neural network.
Proceedings of the 53rd Annual Design Automation Conference, 2016

HW/SW co-design of nonvolatile IO system in energy harvesting sensor nodes for optimal data acquisition.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead.
Proceedings of the 53rd Annual Design Automation Conference, 2016

RRAM based learning acceleration.
Proceedings of the 2016 International Conference on Compilers, 2016

Accurate personal ultraviolet dose estimation with multiple wearable sensors.
Proceedings of the 13th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2016

CP-FPGA: Computation data-aware software/hardware co-design for nonvolatile FPGAs based on checkpointing techniques.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

NVPsim: A simulator for architecture explorations of nonvolatile processors.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Supply-Noise Interactions Among Submodules Inside a Charge-Pump PLL.
IEEE Trans. VLSI Syst., 2015

HS3-DPG: Hierarchical Simulation for 3-D P/G Network.
IEEE Trans. VLSI Syst., 2015

Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis.
IEEE Trans. VLSI Syst., 2015

GPU-Accelerated Sparse LU Factorization for Circuit Simulation with Performance Modeling.
IEEE Trans. Parallel Distrib. Syst., 2015

RRAM-Based Analog Approximate Computing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Multistage Function Speculation Adders.
IEICE Transactions, 2015

A General Scheme for Noise-Tolerant Logic Design Based on Probabilistic and DCVS Approaches.
CoRR, 2015

NXgraph: An Efficient Graph Processing System on a Single Machine.
CoRR, 2015

Drift detection and calibration of sensor networks.
Proceedings of the International Conference on Wireless Communications & Signal Processing, 2015

Design exploration of inrush current aware controller for nonvolatile processor.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

A general scheme for noise-tolerant logic design based on probabilistic and DCVS approaches.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

FASTrust: Feature analysis for third-party IP trust verification.
Proceedings of the 2015 IEEE International Test Conference, 2015

Blind drift calibration of sensor networks using signal space projection and Kalman filter.
Proceedings of the Tenth IEEE International Conference on Intelligent Sensors, 2015

Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

An energy-efficient heterogeneous dual-core processor for Internet of Things.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 5-tissue-layer lumped-element based HBC circuit model compatible to IEEE802.15.6.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Physical computing circuit with no clock to establish Gaussian pyramid of SIFT algorithm.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Energy Efficient RRAM Spiking Neural Network for Real Time Classification.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A self-aware data compression system on FPGA in Hadoop.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

An FPGA-based real-time simultaneous localization and mapping system.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Spiking neural network with RRAM: can we use it for real-world application?
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

From device to system: cross-layer design exploration of racetrack memory.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A fast parallel sparse solver for SPICE-based circuit simulators.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Ambient energy harvesting nonvolatile processors: from circuit to system.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A STT-RAM-based low-power hybrid register file for GPGPUs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Self-powered wearable sensor node: Challenges and opportunities.
Proceedings of the 2015 International Conference on Compilers, 2015

The effects of GND electrodes in capacitive-coupling body channel communication.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

Approximate Computing in Chrominance Cache for Image/Video Processing.
Proceedings of the 2015 IEEE International Conference on Multimedia Big Data, BigMM 2015, 2015

An accurate and low-cost PM2.5 estimation method based on Artificial Neural Network.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Design methodology for approximate accumulator based on statistical error model.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Modeling and optimization of low power resonant clock mesh.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Nonvolatile memory allocation and hierarchy optimization for high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Technological exploration of RRAM crossbar array for matrix-vector multiplication.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors.
IEEE Trans. VLSI Syst., 2014

Hardware Acceleration for an Accurate Stereo Vision System Using Mini-Census Adaptive Support Region.
ACM Trans. Embedded Comput. Syst., 2014

A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ.
IEEE Trans. on Circuits and Systems, 2014

A blind audio watermarking algorithm by logarithmic quantization index modulation.
Multimedia Tools Appl., 2014

On-Chip Hybrid Power Supply System for Wireless Sensor Nodes.
JETC, 2014

Design considerations for low power time-mode SAR ADC.
I. J. Circuit Theory and Applications, 2014

Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects.
IEEE Design & Test, 2014

Low-complexity video encoder for smart eyes based on underdetermined blind signal separation.
CoRR, 2014

Physical Computing With No Clock to Implement the Gaussian Pyramid of SIFT Algorithm.
CoRR, 2014

A high-efficiency dual-channel photovoltaic power system for nonvolatile sensor nodes.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

A single channel, 6-bit 410-ms/s asynchronous SAR ADC based on 3bits/stage.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Efficient region-aware P/G TSV planning for 3D ICs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Energy efficient spiking neural network design with RRAM devices.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A novel quasi-static channel enhancing technique for body channel communication.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Design of multi-stage latency adders using detection and sequence-dependence between successive calculations.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Register allocation for hybrid register architecture in nonvolatile processors.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Large scale recurrent neural network on GPU.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Online scheduling for FPGA computation in the Cloud.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Accelerating frequent item counting with FPGA.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Hardware acceleration with pipelined adder for Support Vector Machine classifier.
Proceedings of the Fourth International Conference on Digital Information and Communication Technology and its Applicationsm DICTAP 2014, 2014

ICE: Inline calibration for memristor crossbar-based computing engine.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy efficient neural networks for big data analytics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Storage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessor.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Training itself: Mixed-signal training acceleration for memristor-based neural network.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Statistical analysis of random telegraph noise in digital circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip.
IEEE Trans. Parallel Distrib. Syst., 2013

A Low-Power Fast-Settling Bond-Wire Frequency Synthesizer With a Dynamic-Bandwidth Scheme.
IEEE Trans. on Circuits and Systems, 2013

NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

MDCT Sinusoidal Analysis for Audio Signals Analysis and Processing.
IEEE Trans. Audio, Speech & Language Processing, 2013

A norm-space, adaptive, and blind audio watermarking algorithm by discrete wavelet transform.
Signal Processing, 2013

Design Methodology of the Heterogeneous Multi-core Processor With the Combination of Parallelized Multi-core Simulator and Common Register File-Based Instruction Set Extension Architecture.
JCP, 2013

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits.
IET Circuits, Devices & Systems, 2013

A novel redundant pipelined successive approximation register ADC.
IEICE Electronic Express, 2013

Assessment of Circuit Optimization Techniques Under NBTI.
IEEE Design & Test, 2013

Increasing Compression Ratio of Low Complexity Compressive Sensing Video Encoder with Application-Aware Configurable Mechanism.
CoRR, 2013

A Novel Reconfigurable Computing Architecture for Image Signal Processing Using Circuit-Switched NoC and Synchronous Dataflow Model.
CoRR, 2013

Nonzero pattern analysis and memory access optimization in GPU-based sparse LU factorization for circuit simulation.
Proceedings of the 3rd Workshop on Irregular Applications - Architectures and Algorithms, 2013

Design of variable latency adder based on present and transitional states prediction.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A Novel Video Compression Method Based on Underdetermined Blind Source Separation.
Proceedings of the Multimedia and Ubiquitous Engineering, 2013

Whitespace-aware TSV arrangement in 3D clock tree synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

TSV-aware topology generation for 3D Clock Tree Synthesis.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Memristor-based approximated computation.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

DTW-Based Subsequence Similarity Search on AMD Heterogeneous Computing Platform.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

Accelerating subsequence similarity search based on dynamic time warping distance with FPGA.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors.
Proceedings of the Design, Automation and Test in Europe, 2013

Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications.
Proceedings of the Design, Automation and Test in Europe, 2013

A low-power robust GFSK demodulation technique for WBAN applications.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

HS3DPG: Hierarchical simulation for 3D P/G network.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization.
IEEE Trans. VLSI Syst., 2012

Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs.
ACM Trans. Design Autom. Electr. Syst., 2012

Design and implementation of motion compensator in memory reduced HDTV decoder with embedded compression engine.
Multimedia Tools Appl., 2012

A "Near-the-Best" System-Level Design Methodology of Multi-Core H.264 Video Decoder Based on the Parallelized Multi-Core Simulator.
Journal of Circuits, Systems, and Computers, 2012

Selective Host-Interference Cancellation: A New Informed Embedding Strategy for Spread Spectrum Watermarking.
IEICE Transactions, 2012

Lifetime-Aware Battery Allocation for Wireless Sensor Network under Cost Constraints.
IEICE Transactions, 2012

Balanced Switching Schemes for Gradient-Error Compensation in Current-Steering DACs.
IEICE Transactions, 2012

A Novel Video Compression Approach Based on Underdetermined Blind Source Separation
CoRR, 2012

A low-complexity symbol-level differential detection scheme for IEEE 802.15.4 O-QPSK signals.
Proceedings of the International Conference on Wireless Communications and Signal Processing, 2012

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An energy harvesting nonvolatile sensor node and its application to distributed moving object detection.
Proceedings of the 11th International Conference on Information Processing in Sensor Networks (co-located with CPS Week 2012), 2012

Probabilistic Brain Fiber Tractography on GPUs.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Parallel Circuit Simulation on Multi/Many-core Systems.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

An informed unipolar spread spectrum modulation for self-synchronized robust watermarking.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

A low-power all-digital GFSK demodulator with robust clock data recovery.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

FPGA based memory efficient high resolution stereo vision system for video tolling.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Pub/Sub on stream: a multi-core based message broker with QoS support.
Proceedings of the Sixth ACM International Conference on Distributed Event-Based Systems, 2012

A compression-based area-efficient recovery architecture for nonvolatile processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Sparse LU factorization for parallel circuit simulation on GPU.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Application specific sensor node architecture optimization - Experiences from field deployments.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A hierarchical C2RTL framework for FIFO-connected stream applications.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

An adaptive LU factorization algorithm for parallel circuit simulation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Power Gating Aware Task Scheduling in MPSoC.
IEEE Trans. VLSI Syst., 2011

Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques.
IEEE Trans. VLSI Syst., 2011

Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.
IEEE Trans. Dependable Sec. Comput., 2011

An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation.
IEEE Trans. on Circuits and Systems, 2011

DFT spectrum estimation from critically sampled lapped transforms.
Signal Processing, 2011

Efficient construction of irregular codes with midterm block length and near-shannon performance.
IET Communications, 2011

A Low-Power IF Circuit with 5 dB Minimum Input SNR for GFSK Low-IF Receivers.
IEICE Transactions, 2011

An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression.
IEICE Transactions, 2011

Mini-step Strategy for Transient Analysis
CoRR, 2011

Circuit-level delay modeling considering both TDDB and NBTI.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Design methodology of multistage time-domain logic speculation circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Low-Power Off-Chip Memory Design for Video Decoder Using Embedded Bus-Invert Coding.
Proceedings of the 10th International Symposium on Autonomous Decentralized Systems, 2011

System-Level Evaluation of Video Processing System Using SimpleScalar-Based Multi-core Processor Simulator.
Proceedings of the 10th International Symposium on Autonomous Decentralized Systems, 2011

Code-independent output impedance: A new approach to increasing the linearity of current-steering DACs.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Gemma in April: A matrix-like parallel programming architecture on OpenCL.
Proceedings of the Design, Automation and Test in Europe, 2011

On-chip hybrid power supply system for wireless sensor nodes.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Evaluation of Tunable Data Compression in Energy-Aware Wireless Sensor Networks.
Sensors, 2010

Output remapping technique for critical paths soft-error rate reduction.
IET Computers & Digital Techniques, 2010

Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting.
IET Circuits, Devices & Systems, 2010

Temperature-Aware Leakage Estimation Using Piecewise Linear Power Models.
IEICE Transactions, 2010

Lightweight Precision-Adaptive Time Synchronization in Wireless Sensor Networks.
IEICE Transactions, 2010

A 250KS/s, 0.8V ultra low power successive approximation register ADC using a Dynamic rail-to-rail comparator.
IEICE Electronic Express, 2010

Transmission Line Inspires A New Distributed Algorithm to Solve the Nonlinear Dynamical System of Physical Circuit
CoRR, 2010

FPGA and GPU implementation of large scale SpMV.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Design methodology of variable latency adders with multistage function speculation.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Making Human Connectome Faster: GPU Acceleration of Brain Network Analysis.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

Maximal Coherence Rotation for stereo coding.
Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010

MDCT spectrum separation: Catching the fine spectral structures for stereo coding.
Proceedings of the IEEE International Conference on Acoustics, 2010

FPMR: MapReduce framework on FPGA.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
Leakage Power Reduction through Dual Vth Assignment Considering Threshold voltage Variation.
Journal of Circuits, Systems, and Computers, 2009

Temperature-Aware NBTI Modeling Techniques in Digital Circuits.
IEICE Transactions, 2009

A novel low power time-mode comparator for successive approximation register ADC.
IEICE Electronic Express, 2009

Waveform Transmission Method, a New Waveform-relaxation Based Algorithm to Solve Ordinary Differential Equations in Parallel
CoRR, 2009

A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design
CoRR, 2009

From devil to angel, transmission lines boost parallel computing of linear resistor networks
CoRR, 2009

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Battery allocation for wireless sensor network lifetime maximization under cost constraints.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Energy efficient architecture of sensor network node based on compression accelerator.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks.
Proceedings of the Design, Automation and Test in Europe, 2009

Gate replacement techniques for simultaneous leakage and aging optimization.
Proceedings of the Design, Automation and Test in Europe, 2009

A case study of on-chip sensor network in multiprocessor system-on-chip.
Proceedings of the 2009 International Conference on Compilers, 2009

2008
Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.
IEEE Trans. VLSI Syst., 2008

A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.
IEEE Trans. VLSI Syst., 2008

Robustness Mode Detection Algorithm in the DRM System.
TBC, 2008

Directed Transmission Method, A Fully Asynchronous Approach to Solve Sparse Linear Systems in Parallel
CoRR, 2008

Virtual Transmission Method, A New Distributed Algorithm to Solve Sparse Linear Systems
CoRR, 2008

Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection.
Science in China Series F: Information Sciences, 2008

Design of Signal Constellations in the Presence of Phase Noise.
Proceedings of the 68th IEEE Vehicular Technology Conference, 2008

Directed transmission method, a fully asynchronous approach to solve sparse linear systems in parallel.
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

Virtual Transmission Method, A New Distributed Algorithm to Solve Sparse Linear Systems.
Proceedings of the NCM 2008, The Fourth International Conference on Networked Computing and Advanced Information Management, Gyeongju, Korea, September 2-4, 2008, 2008

Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Dynamic TDM virtual circuit implementation for NoC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Novel gamma d/n, RLCG Transmission Line Model Considering Complex RC(L) Loads.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Modified Conditional-Precharge Sense-amplifier-Based Flip-Flop with Improved Speed.
Journal of Circuits, Systems, and Computers, 2007

Phase noise analysis of oscillators with Sylvester representation for periodic time-varying modulus matrix by regular perturbations.
Science in China Series F: Information Sciences, 2007

A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Modeling of PMOS NBTI Effect Considering Temperature Variation.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

DRM - the Digital Radio on the Way.
Proceedings of the 12th IEEE Symposium on Computers and Communications (ISCC 2007), 2007

A Noise Reduced Digitally Controlled Oscillator Using Complementary Varactor Pairs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Hybrid Genetic Algorithm with Critical Primary Inputs Sharing and Minor Primary Inputs Bits Climbing for Circuit Maximum Power Estimation.
Proceedings of the Third International Conference on Natural Computation, 2007

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Accurate temperature-dependent integrated circuit leakage power estimation is easy.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
A new adaptive delay method for wideband wireless Kahn's RF power amplifiers.
IEEE Trans. Consumer Electronics, 2006

Signal-Path-Level Dual-VT Assignment for Leakage Power Reduction.
Journal of Circuits, Systems, and Computers, 2006

A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Modeling the Impact of Process Variation on Critical Charge Distribution.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

IR-drop Reduction Through Combinational Circuit Partitioning.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization.
Proceedings of the Advances in Natural Computation, Second International Conference, 2006

A Noise-resilient Channel Estimation Algorithm Based on Two-Dimensional Hadamard Transform for OFDM Systems.
Proceedings of the Fifth International Conference on Networking and the International Conference on Systems (ICN / ICONS / MCL 2006), 2006

Sigma-delta based clock recovery using on-chip PLL in FPGA.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Accurate and Fast Estimation of Junction Band-to-Band Leakage in Nanometer-Scale MOSFET.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET Devices.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Application of DAPSK in HF communications.
IEEE Communications Letters, 2005

Improved Multiuser Detection for Fast FH/MFSK Systems.
Proceedings of the 2005 International Conference on Wireless Networks, 2005

A Robust and Low Complexity Coarse Frequency Offset Estimation Algorithm for DAB Receivers.
Proceedings of the 2005 International Conference on Wireless Networks, 2005

A Hierarchical Approach for Incremental Floorplan Based on Genetic Algorithms.
Proceedings of the Advances in Natural Computation, First International Conference, 2005

Comb-Pattern Optimal Pilot in MIMO-OFDM System.
Proceedings of the Networking and Mobile Computing, Third International Conference, 2005

Gibbs sampling in power grid analysis.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003
Laplacian spectrum analysis and spanning tree algorithm for circuit partitioning problems.
Science in China Series F: Information Sciences, 2003

2002
An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits.
Science in China Series F: Information Sciences, 2002

2001
Noise estimation for deep sub-micron integrated circuits.
Science in China Series F: Information Sciences, 2001

1999
An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999


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