Yi-Hang Chen

According to our database, Yi-Hang Chen authored at least 5 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

Defect-aware synthesis for reconfigurable single-electron transistor arrays.

Juinn-Dar Huang, Yi-Hang Chen, Jia-Shin Lu

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

2016

Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints.

Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang

ACM J. Emerg. Technol. Comput. Syst., 2016

2015

ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays.

Yi-Hang Chen, Yang Chen, Juinn-Dar Huang

Proceedings of the VLSI Design, Automation and Test, 2015

2014

Two-staged parallel layer-aware partitioning for 3D designs.

Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2011

Throughput optimization for latency-insensitive system with minimal queue insertion.

Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011