Yi-Jong Yeh

According to our database, Yi-Jong Yeh authored at least 5 papers between 2001 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

Automatic Partitioner for Behavior Level Distributed Logic Simulation.

Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo

Proceedings of the Formal Techniques for Networked and Distributed Systems, 2005

2004

A Temporal Assertion Extension to Verilog.

Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo

Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

2002

An Optimization-Based Multiple-Voltage Scaling Technique for Low-Power CMOS Digital Design.

Yi-Jong Yeh, Sy-Yen Kuo

J. Circuits Syst. Comput., 2002

2001

Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design.

Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

An optimization-based low-power voltage scaling technique using multiple supply voltages.

Yi-Jong Yeh, Sy-Yen Kuo

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001