Kai-Hui Chang
According to our database1,
Kai-Hui Chang
authored at least 37 papers
between 2004 and 2019.
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Bibliography
2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2016
Handling Nondeterminism in Logic Simulation so That Your Waveform Can Be Trusted Again.
IEEE Des. Test, 2016
2015
Scalable sequence-constrained retention register minimization in power gating design.
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Applying verification intention for design customization via property mining under constrained testbenches.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
ACM Trans. Design Autom. Electr. Syst., 2010
Accurately Handle Don't-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Lecture Notes in Electrical Engineering 32, Springer, ISBN: 978-1-4020-9364-7, 2009
IEEE Des. Test Comput., 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Customizing IP cores for system-on-chip designs using extensive external don't-cares.
Proceedings of the Design, Automation and Test in Europe, 2009
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers.
Proceedings of the 46th Design Automation Conference, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 2008 International Symposium on Physical Design, 2008
2007
PhD thesis, 2007
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2005
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the Formal Techniques for Networked and Distributed Systems, 2005
2004
Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004