Yo-Hwan Koh

According to our database¹, Yo-Hwan Koh authored at least 5 papers between 1996 and 2011.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of five.

Timeline

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PhD thesis

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Bibliography

2011

A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 32Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 48nm 32Gb 8-level NAND flash memory with 5.5MB/s program throughput.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

1996

Offset-trimming bit-line sensing scheme for gigabit-scale DRAM's.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1996

Yo-Hwan Koh

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