Sunghoon Ahn

According to our database¹, Sunghoon Ahn authored at least 8 papers between 2005 and 2014.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2014

19.2 A 93.4mm<sup>2</sup> 64Gb MLC NAND-flash memory with 16nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

2011

A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

2010

A 32Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2005

Differential Pass Transistor Pulsed Latch.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Sunghoon Ahn

Timeline

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Bibliography

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