Yogeswar Reddy Thota

Orcid: 0009-0002-0192-1066

According to our database1, Yogeswar Reddy Thota authored at least 9 papers between 2024 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
When Models Ignore Definitions: Measuring Semantic Override Hallucinations in LLM Reasoning.
CoRR, February, 2026

Human-AI Interaction: Evaluating LLM Reasoning on Digital Logic Circuit included Graph Problems, in terms of creativity in design and analysis.
CoRR, February, 2026

Agentic Hardware Synthesis with CDM Supergatesfor Efficient Design Generation.
Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

SuperGate-Net: CDM-Based MAC for Scalable Neural Inference via Cross-Layer Analysis.
Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

2025
CosineGate: Semantic Dynamic Routing via Cosine Incompatibility in Residual Networks.
CoRR, December, 2025

TinyML Based Biometric Authentication Using PPG Signals for Edge Devices.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

TinyML Enabled Real-Time Bearing Fault Classification in Motors Using Vibration Signals.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

TinyML Based Stress Detection utilizing PPG Signals: A Lightweight Approach for Smart Wearable Devices.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

2024
TinyML for ECG Biometrics on Resource Constrained Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024


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