Yoona Lee

According to our database, Yoona Lee authored at least 5 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A 0.093 pJ/b/dB 20 Gb/s ADC-Based PAM4 Receiver With 33 dB Loss Compensation Using Time-Interleaved Charge-Based Subranging ADC.

Jin-Seok Heo, Yoona Lee, Woo-Seok Choi

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026

HARP: Hadamard-Domain Write-and-Verify for Noise-Robust RRAM Programming.

Ilhuan Choi, Jiwon Yoo, Yoona Lee, Yewon Jeong, Jason Jaesung Lee, Woo-Seok Choi

CoRR, April, 2026

8.8 A 0.292pJ/b 56Gb/s/wire Capacitively Driven Simultaneous Bidirectional Transceiver with PVT/Mismatch Tracking for XSR and D2D Interfaces in 28nm CMOS.

Kahyun Kim, Yoona Lee, Dae-Hoon Na, Ha-Jung Park, Jeongeun Song, Woo-Seok Choi

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

A 2.5-48 Gb/s 16.6 ns Turn-On Time NRZ/PAM4 Pulse-Based Rapid-On/Off Baud-Rate CDR for Mobile Interfaces.

Jihee Kim, Yunhee Lee, Hyun-Seok Choi, Yoona Lee, Sanghee Lee, Woo-Seok Choi

IEEE Trans. Circuits Syst. II Express Briefs, September, 2025

2023

Fast Performance Evaluation Methodology for High-speed Memory Interfaces.

Taehoon Kim, Yoona Lee, Woo-Seok Choi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023