Dae-Hoon Na
Orcid: 0000-0001-9712-2044
According to our database1,
Dae-Hoon Na authored at least 7 papers
between 2015 and 2026.
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Bibliography
2026
A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces.
IEEE J. Solid State Circuits, January, 2026
8.8 A 0.292pJ/b 56Gb/s/wire Capacitively Driven Simultaneous Bidirectional Transceiver with PVT/Mismatch Tracking for XSR and D2D Interfaces in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2023
A 3.0 Gb/s/pin 4<sup>th</sup> generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage.
IEEE J. Solid State Circuits, 2021
2020
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015