Yoshiei Sato

According to our database1, Yoshiei Sato authored at least 4 papers between 2007 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Performance tuning and analysis of future vector processors based on the roofline model.
Proceedings of the 10th workshop on MEmory performance, 2009

2008
A shared cache for a chip multi vector processor.
Proceedings of the 9th workshop on MEmory performance, 2008

Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

2007
An on-chip cache design for vector processors.
Proceedings of the 2007 workshop on MEmory performance, 2007


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