Yoshinobu Ichida

According to our database, Yoshinobu Ichida authored at least 5 papers between 2010 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits.

A. K. M. Mahfuzul Islam, Shinichi Nishizawa, Yusuke Matsui, Yoshinobu Ichida

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2013

Highly Reliable Non-Volatile Logic Circuit Technology and Its Application.

Hiromitsu Kimura, Zhiyong Zhong, Yuta Mizuochi, Norihiro Kinouchi, Yoshinobu Ichida, Yoshikazu Fujimori

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

2012

An Easily Testable Routing Architecture and Prototype Chip.

Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2012

2011

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.

Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

IEICE Trans. Electron., 2011

2010

First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010