Youxiang Chen
Orcid: 0009-0007-4852-7898
According to our database1,
Youxiang Chen authored at least 8 papers
between 2017 and 2026.
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Bibliography
2026
A 108.9dB-DR, 2-2 MASH ADC Featuring a Nested Gainboosting FIA with Gm Enhancement in Settling Phase Through Stepwise Charge Sharing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 105.8-dB DR Continuous-Time Delta-Sigma Modulator with SH-free Quantizer and PVT-adaptive Negative-R.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
A Heterogeneous System With Computing in Memory Processing Elements to Accelerate CNN Inference.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2025
A 5-GSPS continuous-time ΔΣ modulator with nested feedforward compensation OTA and resistive-grounded current-steering DAC achieving 225-MHz bandwidth and 68.5-dB SNR.
Microelectron. J., 2025
An OTA with Series-Cascode-Miller Compensation and Anti-Pole-Splitting for a 360-MHz BW Low-Distortion TIA in Sub-6G Broadband RF Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
RSACIM: Resistance Summation Analog Computing in Memory With Accuracy Optimization Scheme Based on MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
FRM-CIM: Full-Digital Recursive MAC Computing in Memory System Based on MRAM for Neural Network Applications.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2017
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs.
Proceedings of the 54th Annual Design Automation Conference, 2017