Kun Zhang

Orcid: 0000-0001-7215-7953

Affiliations:

Beihang University, Fert Beijing Research Institute, Beijing, China
Beihang University, Qingdao Research Institute, Beihang-Goertek Joint Microelectronics Institute, China
Shandong University, Department of Physics, Jinan, China (PhD 2017)

According to our database¹, Kun Zhang authored at least 14 papers between 2019 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Bibliography

2025

A Heterogeneous System With Computing in Memory Processing Elements to Accelerate CNN Inference.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2025

HRAMTran: A Hybrid-RAM Transformer Accelerator With Dynamic Sparsity Floating-Point CIM and Written-Back Transpose Array.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

2024

RSACIM: Resistance Summation Analog Computing in Memory With Accuracy Optimization Scheme Based on MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2023

Implementation of 16 Boolean logic operations based on one basic cell of spin-transfer-torque magnetic random access memory.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., June, 2023

Magnetic coupling governed pinning directions in magnetic tunnel junctions under magnetic field annealing with zero magnetic field cooling.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., April, 2023

2022

Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance Computing in Memory Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network.

[BibT_eX]

[DOI]

Georgios Ch. Sirakoulis

Youguang Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic.

[BibT_eX]

[DOI]

IEEE Access, 2020

Efficient Time-Domain In-Memory Computing Based on TST-MRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Kun Zhang

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