Yue Zhang

Orcid: 0000-0001-6893-7199

Affiliations:
  • Beihang University, Fert Beijing Institute, Beijing, China
  • University of Paris-Sud, Orsay, France (PhD 2014)


According to our database1, Yue Zhang authored at least 48 papers between 2011 and 2024.

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Bibliography

2024
A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

RSACIM: Resistance Summation Analog Computing in Memory With Accuracy Optimization Scheme Based on MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2023
A Novel 9T1C-SRAM Compute-In-Memory Macro With Count-Less Pulse-Width Modulation Input and ADC-Less Charge-Integration-Count Output.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

Reinforcement Learning-assisted Evolutionary Algorithm: A Survey and Research Opportunities.
CoRR, 2023

TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance Computing in Memory Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Memristor Crossbar Arrays Performing Quantum Algorithms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021
Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

2020
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM.
IEEE Trans. Circuits Syst., 2020

A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic.
IEEE Access, 2020

Efficient Time-Domain In-Memory Computing Based on TST-MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

2018
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

A true random number generator based on parallel STT-MTJs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron.
IEEE Trans. Biomed. Circuits Syst., 2016

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectron. Reliab., 2016

Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Compact thermal modeling of spin transfer torque magnetic tunnel junction.
Microelectron. Reliab., 2015

Tunnel Junction with Perpendicular Magnetic Anisotropy: Status and Challenges.
Micromachines, 2015

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.
ACM J. Emerg. Technol. Comput. Syst., 2015

Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

From device to system: cross-layer design exploration of racetrack memory.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectron. Reliab., 2014

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput., 2014

Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Spintronics for low-power computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An overview of spin-based integrated circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Magnetic Adder Based on Racetrack Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectron. Reliab., 2013

Spin-electronics based logic fabrics.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Synchronous full-adder based on complementary resistive switching memory cells.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Low power magnetic flip-flop based on checkpointing and self-enable mechanism.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Analytical study of complementary memristive synchronous logic gates.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

2012
Failure and reliability analysis of STT-MRAM.
Microelectron. Reliab., 2012

Crossbar architecture based on 2R complementary resistive switching memory cell.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

2011
Embedded MRAM for high-speed computing.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

High Performance SoC Design Using Magnetic Logic and Memory.
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011


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