Yu-Kai Chou

According to our database¹, Yu-Kai Chou authored at least 3 papers between 2008 and 2017.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2017

A Time-Interleaved Statistically-Driven Two-Step Flash ADC for High-Speed Wireline Applications.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2017

2014

A power management unit integrated ADSL/ADSL2+ CPE analog front-end with -93.5dB THD for DMT-based applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2008

A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Yu-Kai Chou

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