Yu-Liang Chou

According to our database, Yu-Liang Chou authored at least 17 papers between 2008 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Counterfactuals and causability in explainable artificial intelligence: Theory, algorithms, and applications.

Yu-Liang Chou, Catarina Moreira, Peter Bruza, Chun Ouyang, Joaquim A. Jorge

Inf. Fusion, 2022

Benchmark Evaluation of Counterfactual Algorithms for XAI: From a White Box to a Black Box.

Yu-Liang Chou, Chihcheng Hsieh, Catarina Moreira, Chun Ouyang, Joaquim A. Jorge, João Madeiras Pereira

CoRR, 2022

2021

LINDA-BN: An interpretable probabilistic approach for demystifying black-box predictive models.

Catarina Moreira, Yu-Liang Chou, Mythreyi Velmurugan, Chun Ouyang, Renuka Sindhgatta, Peter Bruza

Decis. Support Syst., 2021

2020

An Interpretable Probabilistic Approach for Demystifying Black-box Predictive Models.

Catarina Moreira, Yu-Liang Chou, Mythreyi Velmurugan, Chun Ouyang, Renuka Sindhgatta, Peter Bruza

CoRR, 2020

2014

An Energy and Performance Efficient DVFS Scheme for Irregular Parallel Divide-and-Conquer Algorithms on the Intel SCC.

Yu-Liang Chou, Shaoshan Liu, Eui-Young Chung, Jean-Luc Gaudiot

IEEE Comput. Archit. Lett., 2014

2013

A hyperscalar dual-core architecture for embedded systems.

Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou

Microprocess. Microsystems, 2013

A relation-exchanging buffering mechanism for instruction and data streaming.

Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou, Chih-Kang Wu

Comput. Electr. Eng., 2013

OCP: Offload Co-Processor for energy efficiency in embedded mobile systems.

Jie Tang, Chen Liu, Yu-Liang Chou, Shaoshan Liu

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2011

A Unitable Computing Architecture for Chip Multiprocessors.

Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen, Ding-Siang Su

Comput. J., 2011

2010

A multi-streaming SIMD multimedia computing engine.

Jih-Ching Chiu, Yu-Liang Chou

Microprocess. Microsystems, 2010

The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA.

Jih-Ching Chiu, Yu-Liang Chou, Tseng-Kuei Lin

J. Inf. Sci. Eng., 2010

Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture.

Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen

Proceedings of the 39th International Conference on Parallel Processing, 2010

A hyperscalar multi-core architecture.

Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su

Proceedings of the 7th Conference on Computing Frontiers, 2010

2009

Design of a novel SIMD architecture by fusing operations and registers.

Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou

Proceedings of the 23rd international conference on Supercomputing, 2009

A multi-streaming SIMD architecture for multimedia applications.

Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng

Proceedings of the 6th Conference on Computing Frontiers, 2009

2008

The Multi-context Reconfigurable Processing Unit for Fine-grain Computing.

Jih-Ching Chiu, Yu-Liang Chou, Ren-Bang Lin

J. Inf. Sci. Eng., 2008

Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA.

Jih-Ching Chiu, Yu-Liang Chou, Ta-Li Yeh, Tseng-Kuei Lin

Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008