Yu Wang

Orcid: 0000-0002-9345-4911

Affiliations:
  • University of California Santa Barbara, Department of Electrical and Computer Engineering, Santa Barbara, CA, USA
  • Texas A&M University, College Station, TX, USA (until 2019)


According to our database1, Yu Wang authored at least 11 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
Contrastive Learning with Consistent Representations.
Trans. Mach. Learn. Res., 2024

Extreme Risk Mitigation in Reinforcement Learning using Extreme Value Theory.
Trans. Mach. Learn. Res., 2024

Towards the Mitigation of Confirmation Bias in Semi-supervised Learning: a Debiased Training Perspective.
CoRR, 2024

High-Dimensional Bayesian Optimization via Semi-Supervised Learning with Optimized Unlabeled Data Sampling.
Proceedings of the Forty-first International Conference on Machine Learning, 2024

ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Semi-supervised Learning of Dynamical Systems with Neural Ordinary Differential Equations: A Teacher-Student Model Approach.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
Contrastive Learning with Consistent Representations.
CoRR, 2023

AutoNF: Automated Architecture Optimization of Normalizing Flows with Unconstrained Continuous Relaxation Admitting Optimal Discrete Solution.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2021
Algorithm and Hardware Co-Design for FPGA Acceleration of Hamiltonian Monte Carlo Based No-U-Turn Sampler.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
A Scalable FPGA Engine for Parallel Acceleration of Singular Value Decomposition.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2017
A clock interpolation structure using DLL for clock distribution in ADC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017


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