Yucong Huang

Orcid: 0000-0002-8499-4254

According to our database1, Yucong Huang authored at least 24 papers between 2015 and 2026.

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Bibliography

2026
RV-WINO: A RISC-V Neural Network Accelerator Based on Winograd Algorithm Fabricated in 55-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst., May, 2026

Transitivity Meets Cyclicity: Explicit Preference Decomposition for Dynamic Large Language Model Alignment.
CoRR, May, 2026

CreativeGame:Toward Mechanic-Aware Creative Game Generation.
CoRR, April, 2026

TranCAD: Transforming tabular data into color images for deep semi-supervised anomaly detection.
Expert Syst. Appl., 2026

Model-Based Imaginative Planning for Embodied Agents.
Proceedings of the 64th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), 2026

2025
A Two-Stage Day-Ahead Multi-Energy Consumption Forecasting Method Based on Multi-Task Spatiotemporal Coupling Informer and Enhanced Spider Wasp Optimization.
IEEE Trans. Smart Grid, November, 2025

RV-SCNN: A RISC-V Processor With Customized Instruction Set for SNN and CNN Inference Acceleration on Edge Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2025

IGFNet: An Interactive-Guided Fusion Network for Hyperspectral Pansharpening.
IEEE Trans. Geosci. Remote. Sens., 2025

MSADNet: Multi-Scale Adaptive Dual Attention Network for Multivariate Time Series Anomaly Detection.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2025

NNia-8: An 8-Core RISC-V Neural Network Inference Accelerator with Efficient Processing Elements and Memory Utilization.
Proceedings of the Network and Parallel Computing, 2025

A Low-Noise, High-Input-Impedance Pre-Amplifier for Piezoelectric MEMS Microphone.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Fusion-PSRO: Nash Policy Fusion for Policy Space Response Oracles.
Proceedings of the ECAI 2025 - 28th European Conference on Artificial Intelligence, 25-30 October 2025, Bologna, Italy, 2025

Logic Gate Network Inference Acceleration with RISC-V Custom Instruction Set.
Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025

2024
Conflux-PSRO: Effectively Leveraging Collective Advantages in Policy Space Response Oracles.
CoRR, 2024

Fusion-PSRO: Nash Policy Fusion for Policy Space Response Oracles.
CoRR, 2024

RWriC: A Dynamic Writing Scheme for Variation Compensation for RRAM-based In-Memory Computing.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

RV-GEMM: Neural Network Inference Acceleration with Near-Memory GEMM Instructions on RISC-V.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

RISCV-FNT: A Fast FNT-based RISC-V Processor for CNN Acceleration.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
RVComp: Analog Variation Compensation for RRAM-Based in-Memory Computing.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2021
55nm CMOS Analog Circuit Implementation of LIF and STDP Functions for Low-Power SNNs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

2020
Analog Circuit Implementation of LIF and STDP Models for Spiking Neural Networks.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Analog Circuit Implementation of Neurons with Multiply-Accumulate and ReLU Functions.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019
Analog Implementation of Reconfigurable Convolutional Neural Network Kernels.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2015
Enhanced DCTCP to explicitly inform of packet loss.
Proceedings of the 2015 IEEE International Conference on Communications, 2015


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